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Differential D60065

[AArch64] Add v8.5-a Memory Tagging STZGM instruction
ClosedPublic

Authored by DavidSpickett on Apr 1 2019, 6:44 AM.

Details

Reviewers
javed.absar
Commits
rG3d233d5d4d82: [AArch64] Add v8.5-a Memory Tagging STZGM instruction
rL357397: [AArch64] Add v8.5-a Memory Tagging STZGM instruction
Summary

This instruction writes a block of allocation tags
and stores zero to the associated data locations.

It differs from STGM by 1 bit and has the same
arguments.

The specification can be found here:
https://developer.arm.com/docs/ddi0596/c

Diff Detail

Repository
rL LLVM

Event Timeline

DavidSpickett created this revision.Apr 1 2019, 6:44 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 1 2019, 6:44 AM
Herald added subscribers: llvm-commits, kristof.beyls, javed.absar. · View Herald Transcript
DavidSpickett added a reviewer: javed.absar.Apr 1 2019, 6:45 AM
javed.absar accepted this revision.Apr 1 2019, 7:23 AM
This revision is now accepted and ready to land.Apr 1 2019, 7:23 AM
Closed by commit rL357397: [AArch64] Add v8.5-a Memory Tagging STZGM instruction (authored by DavidSpickett). · Explain WhyApr 1 2019, 7:58 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
4 lines
test/
MC/
AArch64/
23 lines
14 lines
Disassembler/
AArch64/
12 lines

Diff 193090

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">; def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">;
def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>; def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>;
def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]", def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]",
(outs GPR64:$Rt), (ins GPR64sp:$Rn)>; (outs GPR64:$Rt), (ins GPR64sp:$Rn)>;
def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]", def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",
(outs), (ins GPR64:$Rt, GPR64sp:$Rn)>; (outs), (ins GPR64:$Rt, GPR64sp:$Rn)>;
def STZGM : MemTagVector<0, "stzgm", "\t$Rt, [$Rn]",
(outs), (ins GPR64:$Rt, GPR64sp:$Rn)> {
let Inst{23} = 0;
}
defm STG : MemTagStore<0b00, "stg">; defm STG : MemTagStore<0b00, "stg">;
defm STZG : MemTagStore<0b01, "stzg">; defm STZG : MemTagStore<0b01, "stzg">;
defm ST2G : MemTagStore<0b10, "st2g">; defm ST2G : MemTagStore<0b10, "st2g">;
defm STZ2G : MemTagStore<0b11, "stz2g">; defm STZ2G : MemTagStore<0b11, "stz2g">;
defm STGP : StorePairOffset <0b01, 0, GPR64z, simm7s16, "stgp">; defm STGP : StorePairOffset <0b01, 0, GPR64z, simm7s16, "stgp">;
def STGPpre : StorePairPreIdx <0b01, 0, GPR64z, simm7s16, "stgp">; def STGPpre : StorePairPreIdx <0b01, 0, GPR64z, simm7s16, "stgp">;
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llvm/trunk/test/MC/AArch64/armv8.5a-mte-error.s

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// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stgm w0, [x0] // CHECK-NEXT: stgm w0, [x0]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stgm x0, [w0] // CHECK-NEXT: stgm x0, [w0]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stgm #1, [x1] // CHECK-NEXT: stgm #1, [x1]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stgm x0, [#1] // CHECK-NEXT: stgm x0, [#1]
stzgm
stzgm x0
stzgm sp, [x0]
stzgm w0, [x0]
stzgm x0, [w0]
stzgm #1, [x1]
stzgm x0, [#1]
// CHECK: too few operands for instruction
// CHECK-NEXT: stzgm
// CHECK: too few operands for instruction
// CHECK-NEXT: stzgm x0
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzgm sp, [x0]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzgm w0, [x0]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzgm x0, [w0]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzgm #1, [x1]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzgm x0, [#1]

llvm/trunk/test/MC/AArch64/armv8.5a-mte.s

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ldgm xzr, [x2] ldgm xzr, [x2]
// CHECK: ldgm x0, [x1] // encoding: [0x20,0x00,0xe0,0xd9] // CHECK: ldgm x0, [x1] // encoding: [0x20,0x00,0xe0,0xd9]
// CHECK: ldgm x1, [sp] // encoding: [0xe1,0x03,0xe0,0xd9] // CHECK: ldgm x1, [sp] // encoding: [0xe1,0x03,0xe0,0xd9]
// CHECK: ldgm xzr, [x2] // encoding: [0x5f,0x00,0xe0,0xd9] // CHECK: ldgm xzr, [x2] // encoding: [0x5f,0x00,0xe0,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte
stgm x0, [x1] stgm x0, [x1]
stgm x1, [sp] stgm x1, [sp]
stgm xzr, [x2] stgm xzr, [x2]
// CHECK: stgm x0, [x1] // encoding: [0x20,0x00,0xa0,0xd9] // CHECK: stgm x0, [x1] // encoding: [0x20,0x00,0xa0,0xd9]
// CHECK: stgm x1, [sp] // encoding: [0xe1,0x03,0xa0,0xd9] // CHECK: stgm x1, [sp] // encoding: [0xe1,0x03,0xa0,0xd9]
// CHECK: stgm xzr, [x2] // encoding: [0x5f,0x00,0xa0,0xd9] // CHECK: stgm xzr, [x2] // encoding: [0x5f,0x00,0xa0,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte
stzgm x0, [x1]
stzgm x1, [sp]
stzgm xzr, [x2]
// CHECK: stzgm x0, [x1] // encoding: [0x20,0x00,0x20,0xd9]
// CHECK: stzgm x1, [sp] // encoding: [0xe1,0x03,0x20,0xd9]
// CHECK: stzgm xzr, [x2] // encoding: [0x5f,0x00,0x20,0xd9]
// NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte
// NOMTE: instruction requires: mte

llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt

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# NOMTE-NEXT: [0x83,0xf0,0x6f,0xd9] # NOMTE-NEXT: [0x83,0xf0,0x6f,0xd9]
[0x20,0x00,0xe0,0xd9] [0x20,0x00,0xe0,0xd9]
[0xe1,0x03,0xe0,0xd9] [0xe1,0x03,0xe0,0xd9]
[0x5f,0x00,0xe0,0xd9] [0x5f,0x00,0xe0,0xd9]
[0x20,0x00,0xa0,0xd9] [0x20,0x00,0xa0,0xd9]
[0xe1,0x03,0xa0,0xd9] [0xe1,0x03,0xa0,0xd9]
[0x5f,0x00,0xa0,0xd9] [0x5f,0x00,0xa0,0xd9]
[0x20,0x00,0x20,0xd9]
[0xe1,0x03,0x20,0xd9]
[0x5f,0x00,0x20,0xd9]
# CHECK: ldgm x0, [x1] # CHECK: ldgm x0, [x1]
# CHECK: ldgm x1, [sp] # CHECK: ldgm x1, [sp]
# CHECK: ldgm xzr, [x2] # CHECK: ldgm xzr, [x2]
# CHECK: stgm x0, [x1] # CHECK: stgm x0, [x1]
# CHECK: stgm x1, [sp] # CHECK: stgm x1, [sp]
# CHECK: stgm xzr, [x2] # CHECK: stgm xzr, [x2]
# CHECK: stzgm x0, [x1]
# CHECK: stzgm x1, [sp]
# CHECK: stzgm xzr, [x2]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x20,0x00,0xe0,0xd9] # NOMTE-NEXT: [0x20,0x00,0xe0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xe1,0x03,0xe0,0xd9] # NOMTE-NEXT: [0xe1,0x03,0xe0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0x00,0xe0,0xd9] # NOMTE-NEXT: [0x5f,0x00,0xe0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x20,0x00,0xa0,0xd9] # NOMTE-NEXT: [0x20,0x00,0xa0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xe1,0x03,0xa0,0xd9] # NOMTE-NEXT: [0xe1,0x03,0xa0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0x00,0xa0,0xd9] # NOMTE-NEXT: [0x5f,0x00,0xa0,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x20,0x00,0x20,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xe1,0x03,0x20,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0x00,0x20,0xd9]
[0x60,0x76,0x08,0xd5] [0x60,0x76,0x08,0xd5]
[0x81,0x76,0x08,0xd5] [0x81,0x76,0x08,0xd5]
[0x82,0x7a,0x08,0xd5] [0x82,0x7a,0x08,0xd5]
[0x83,0x7e,0x08,0xd5] [0x83,0x7e,0x08,0xd5]
[0x64,0x7a,0x0b,0xd5] [0x64,0x7a,0x0b,0xd5]
[0x65,0x7c,0x0b,0xd5] [0x65,0x7c,0x0b,0xd5]
[0x66,0x7d,0x0b,0xd5] [0x66,0x7d,0x0b,0xd5]
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