[AArch64] Add v8.5-a Memory Tagging GMID_EL1 register

[DavidSpickett]

Summary

The latest version of the MTE spec added a system
register 'GMID_EL1'. It contains the block size used
by the LDGM and STGM instructions and is read only.

The specification can be found here:
https://developer.arm.com/docs/ddi0596/c

[javed.absar]

LGTM , except for a small nitpick.

test/MC/AArch64/armv8.5a-mte-error.s

681

unnecessary comment

lib/Target/AArch64/AArch64SystemOperands.td

 def : RWSysReg<"TCO",              0b11, 0b011, 0b0100, 0b0010, 0b111>;
 def : RWSysReg<"GCR_EL1",          0b11, 0b000, 0b0001, 0b0000, 0b110>;
 def : RWSysReg<"RGSR_EL1",         0b11, 0b000, 0b0001, 0b0000, 0b101>;
 def : RWSysReg<"TFSR_EL1",         0b11, 0b000, 0b0110, 0b0101, 0b000>;
 def : RWSysReg<"TFSR_EL2",         0b11, 0b100, 0b0110, 0b0101, 0b000>;
 def : RWSysReg<"TFSR_EL3",         0b11, 0b110, 0b0110, 0b0110, 0b000>;
 def : RWSysReg<"TFSR_EL12",        0b11, 0b101, 0b0110, 0b0110, 0b000>;
 def : RWSysReg<"TFSRE0_EL1",       0b11, 0b000, 0b0110, 0b0110, 0b001>;
+def : ROSysReg<"GMID_EL1",         0b11, 0b001, 0b0000, 0b0000, 0b100>;
 } // HasMTE
 
 // Cyclone specific system registers
 //                                 Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::ProcCyclone} }] in
 def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>;

test/MC/AArch64/armv8.5a-mte-error.s

 mrs tco
 mrs gcr_el1
 mrs rgsr_el1
 mrs tfsr_el1
 mrs tfsr_el2
 mrs tfsr_el3
 mrs tfsr_el12
 mrs tfsre0_el1
+mrs gmid_el1
 
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tco
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: gcr_el1
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: rgsr_el1
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsr_el1
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsr_el2
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsr_el3
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsr_el12
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsre0_el1
+// CHECK:      invalid operand for instruction
+// CHECK-NEXT: gmid_el1
 
 mrs tco, #0
 mrs tco, x0
 mrs gcr_el1, x1
 mrs rgsr_el1, x2
 mrs tfsr_el1, x3
 mrs tfsr_el2, x4
 mrs tfsr_el3, x5
 mrs tfsr_el12, x6
 mrs tfsre0_el1, x7
+mrs gmid_el1, x7
 
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tco, #0
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tco, x0
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: gcr_el1
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: rgsr_el1
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsr_el1
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsr_el2
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsr_el3
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsr_el12
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsre0_el1
+// CHECK:      invalid operand for instruction
+// CHECK-NEXT: gmid_el1
 
 msr tco
 msr gcr_el1
 msr rgsr_el1
 msr tfsr_el1
 msr tfsr_el2
 msr tfsr_el3
 msr tfsr_el12
 msr tfsre0_el1
+msr gmid_el1
 
 // CHECK:      too few operands for instruction
 // CHECK-NEXT: tco
 // CHECK:      too few operands for instruction
 // CHECK-NEXT: gcr_el1
 // CHECK:      too few operands for instruction
 // CHECK-NEXT: rgsr_el1
 // CHECK:      too few operands for instruction
 // CHECK-NEXT: tfsr_el1
 // CHECK:      too few operands for instruction
 // CHECK-NEXT: tfsr_el2
 // CHECK:      too few operands for instruction
 // CHECK-NEXT: tfsr_el3
 // CHECK:      too few operands for instruction
 // CHECK-NEXT: tfsr_el12
 // CHECK:      too few operands for instruction
 // CHECK-NEXT: tfsre0_el1
+// CHECK:      expected writable system register or pstate
+// CHECK-NEXT: gmid_el1
 
 msr x0, tco
 msr x1, gcr_el1
 msr x2, rgsr_el1
 msr x3, tfsr_el1
 msr x4, tfsr_el2
 msr x5, tfsr_el3
 msr x6, tfsr_el12
 msr x7, tfsre0_el1
+msr x7, gmid_el1
 
 // CHECK:      expected writable system register or pstate
 // CHECK-NEXT: tco
 // CHECK:      expected writable system register or pstate
 // CHECK-NEXT: gcr_el1
 // CHECK:      expected writable system register or pstate
 // CHECK-NEXT: rgsr_el1
 // CHECK:      expected writable system register or pstate
 // CHECK-NEXT: tfsr_el1
 // CHECK:      expected writable system register or pstate
 // CHECK-NEXT: tfsr_el2
 // CHECK:      expected writable system register or pstate
 // CHECK-NEXT: tfsr_el3
 // CHECK:      expected writable system register or pstate
 // CHECK-NEXT: tfsr_el12
 // CHECK:      expected writable system register or pstate
 // CHECK-NEXT: tfsre0_el1
+// CHECK:      expected writable system register or pstate
+// CHECK-NEXT: gmid_el1
+
+msr gmid_el1, x7
+
+// CHECK:      expected writable system register or pstate
+// CHECK-NEXT: gmid_el1
 
 // Among the system registers added by MTE, only TCO can be used with MSR (imm).
 // The rest can only be used with MSR (reg).
 msr gcr_el1, #1
 msr rgsr_el1, #2
 msr tfsr_el1, #3
 msr tfsr_el2, #4
 msr tfsr_el3, #5
 msr tfsr_el12, #6
 msr tfsre0_el1, #7
+// Is read only
+msr gmid_el1, #7
 
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: gcr_el1
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: rgsr_el1
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsr_el1
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsr_el2
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsr_el3
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsr_el12
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: tfsre0_el1
+// CHECK:      expected writable system register or pstate
+// CHECK-NEXT: gmid_el1
 
 // Xd cannot be the stack pointer, the rest can
 subps sp, x0, x1
 subp  sp, x2, x3
 subp  w0, x1, x2
 subp  x0, w1, x2
 subp  x0, x1, w2
 subps w0, x1, x2

test/MC/AArch64/armv8.5a-mte.s

 mrs x0, tco
 mrs x1, gcr_el1
 mrs x2, rgsr_el1
 mrs x3, tfsr_el1
 mrs x4, tfsr_el2
 mrs x5, tfsr_el3
 mrs x6, tfsr_el12
 mrs x7, tfsre0_el1
+mrs x7, gmid_el1
 
 // CHECK: mrs x0, TCO           // encoding: [0xe0,0x42,0x3b,0xd5]
 // CHECK: mrs x1, GCR_EL1       // encoding: [0xc1,0x10,0x38,0xd5]
 // CHECK: mrs x2, RGSR_EL1      // encoding: [0xa2,0x10,0x38,0xd5]
 // CHECK: mrs x3, TFSR_EL1      // encoding: [0x03,0x65,0x38,0xd5]
 // CHECK: mrs x4, TFSR_EL2      // encoding: [0x04,0x65,0x3c,0xd5]
 // CHECK: mrs x5, TFSR_EL3      // encoding: [0x05,0x66,0x3e,0xd5]
 // CHECK: mrs x6, TFSR_EL12     // encoding: [0x06,0x66,0x3d,0xd5]
 // CHECK: mrs x7, TFSRE0_EL1    // encoding: [0x27,0x66,0x38,0xd5]
+// CHECK: mrs x7, GMID_EL1      // encoding: [0x87,0x00,0x39,0xd5]
 
 // NOMTE: expected readable system register
 // NOMTE-NEXT: tco
 // NOMTE: expected readable system register
 // NOMTE-NEXT: gcr_el1
 // NOMTE: expected readable system register
 // NOMTE-NEXT: rgsr_el1
 // NOMTE: expected readable system register
 // NOMTE-NEXT: tfsr_el1
 // NOMTE: expected readable system register
 // NOMTE-NEXT: tfsr_el2
 // NOMTE: expected readable system register
 // NOMTE-NEXT: tfsr_el3
 // NOMTE: expected readable system register
 // NOMTE-NEXT: tfsr_el12
 // NOMTE: expected readable system register
 // NOMTE-NEXT: tfsre0_el1
+// NOMTE: expected readable system register
+// NOMTE-NEXT: gmid_el1
 
 msr tco, #0
 
 // CHECK: msr TCO, #0           // encoding: [0x9f,0x40,0x03,0xd5]
 
 // NOMTE: expected writable system register or pstate
 // NOMTE-NEXT: tco
 

test/MC/Disassembler/AArch64/armv8.5a-mte.txt

 [0xe0,0x42,0x3b,0xd5]
 [0xc1,0x10,0x38,0xd5]
 [0xa2,0x10,0x38,0xd5]
 [0x03,0x65,0x38,0xd5]
 [0x04,0x65,0x3c,0xd5]
 [0x05,0x66,0x3e,0xd5]
 [0x06,0x66,0x3d,0xd5]
 [0x27,0x66,0x38,0xd5]
+[0x88,0x00,0x39,0xd5]
 
 # CHECK: mrs x0, TCO
 # CHECK: mrs x1, GCR_EL1
 # CHECK: mrs x2, RGSR_EL1
 # CHECK: mrs x3, TFSR_EL1
 # CHECK: mrs x4, TFSR_EL2
 # CHECK: mrs x5, TFSR_EL3
 # CHECK: mrs x6, TFSR_EL12
 # CHECK: mrs x7, TFSRE0_EL1
+# CHECK: mrs x8, GMID_EL1
 
 # NOMTE: mrs x0, S3_3_C4_C2_7
 # NOMTE: mrs x1, S3_0_C1_C0_6
 # NOMTE: mrs x2, S3_0_C1_C0_5
 # NOMTE: mrs x3, S3_0_C6_C5_0
 # NOMTE: mrs x4, S3_4_C6_C5_0
 # NOMTE: mrs x5, S3_6_C6_C6_0
 # NOMTE: mrs x6, S3_5_C6_C6_0
 # NOMTE: mrs x7, S3_0_C6_C6_1
+# NOMTE: mrs x8, S3_1_C0_C0_4
 
 [0x9f,0x40,0x03,0xd5]
 
 # CHECK: msr TCO, #0
 # NOMTE: msr S0_3_C4_C0_4, xzr
 
 [0xe0,0x42,0x1b,0xd5]
 [0xc1,0x10,0x18,0xd5]
 [0xa2,0x10,0x18,0xd5]
 [0x03,0x65,0x18,0xd5]
 [0x04,0x65,0x1c,0xd5]
 [0x05,0x66,0x1e,0xd5]
 [0x06,0x66,0x1d,0xd5]
 [0x27,0x66,0x18,0xd5]
+[0x88,0x00,0x19,0xd5]
 
 # CHECK: msr TCO, x0
 # CHECK: msr GCR_EL1, x1
 # CHECK: msr RGSR_EL1, x2
 # CHECK: msr TFSR_EL1, x3
 # CHECK: msr TFSR_EL2, x4
 # CHECK: msr TFSR_EL3, x5
 # CHECK: msr TFSR_EL12, x6
 # CHECK: msr TFSRE0_EL1, x7
+# GMID_EL1 is read only
+# CHECK: msr S3_1_C0_C0_4, x8
 
 # NOMTE: msr S3_3_C4_C2_7, x0
 # NOMTE: msr S3_0_C1_C0_6, x1
 # NOMTE: msr S3_0_C1_C0_5, x2
 # NOMTE: msr S3_0_C6_C5_0, x3
 # NOMTE: msr S3_4_C6_C5_0, x4
 # NOMTE: msr S3_6_C6_C6_0, x5
 # NOMTE: msr S3_5_C6_C6_0, x6
 # NOMTE: msr S3_0_C6_C6_1, x7
+# NOMTE: msr S3_1_C0_C0_4, x8