AMDGPU: RETURNADDR lowering

[aakanksha555]

Summary

Patch to do return address lowering.

[arsenm]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2793–2795

verifyReturnAddressArgumentIsConstant should probably be removed in a separate patch. The verifier now rejects the IR, and the DAG should never be allowed to produce an invalid one

2799–2801

Unnecessary comment

2807–2810

This should not be an assert. According to the spec, this could just return 0 for another frame id

2815

Should use TRI::getReturnAddressReg rather than hardcoding it in another place. You can just hardcode the register class though

test/CodeGen/AMDGPU/returnaddress.ll

2

Should use HSA triple

10

Use named values

13

Needs test with non-0 frame

[arsenm]

Commit message should also say it's lowering returnaddress, not mention instrument-functions

[arsenm]

test/CodeGen/AMDGPU/returnaddress.ll

8

Needs a test with amdgpu_kernel and shaders. As is this will fail as they don’t have return addresses

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

4156

Formatting

4159–4161

This can just give 0 instead of erring

4168

This still won't handle kernels correctly

test/CodeGen/AMDGPU/returnaddress.ll

19

Needs tests with a kernel and shader, since this should crash as is since there is no return address

[arsenm]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

29

Not sure why you need a new include here

[aakanksha555]

Return 0 for kernels and non-zero arguments to llvm.returnaddress.

[arsenm]

Mostly LGTM, but 2 more test cases might be useful; one with no ret, and one with the use outside of the entry block

[aakanksha555]

Added a test outside entry block; doesn't make any difference in the output.
By a test with no ret, do you mean something that returns void?

[aakanksha555]

Minor changes in one of the tests.

[arsenm]

In D59666#1502063, @aakanksha555 wrote:

Added a test outside entry block; doesn't make any difference in the output.
By a test with no ret, do you mean something that returns void?

No, I mean ends in unreachable

test/CodeGen/AMDGPU/returnaddress.ll

48–50

This is still in the entry block

[aakanksha555]

Fixed two tests; one which does not return and another with use outside of the entry block.

[arsenm]

returnadr.diff

2 ↗

(On Diff #201329)

You somehow added the diff as a file

105 ↗

(On Diff #201329)

The call is still in the entry block. You should also make it a conditional branch to make sure nothing folds it

test/CodeGen/AMDGPU/returnaddress.ll

43–44

The call is still in the entry block. You should also make it a conditional branch to make sure nothing folds it

[aakanksha555]

Fix in one of the tests.

[arsenm]

LGTM

test/CodeGen/AMDGPU/returnaddress.ll

61–63

This can just be one block

lib/Target/AMDGPU/AMDGPUISelLowering.h

 
   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
 
+  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
+
 protected:
   bool shouldCombineMemoryType(EVT VT) const;
   SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 #include "Utils/AMDGPUBaseInfo.h"
 #include "R600MachineFunctionInfo.h"
 #include "SIInstrInfo.h"
+#include "SIRegisterInfo.h"
 #include "SIMachineFunctionInfo.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "llvm/CodeGen/Analysis.h"

lib/Target/AMDGPU/SIISelLowering.h

   SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
-
+  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
                               SelectionDAG &DAG, ArrayRef<SDValue> Ops,
                               bool IsIntrinsic = false) const;

lib/Target/AMDGPU/SIISelLowering.cpp

   switch (Op.getOpcode()) {
   default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
   case ISD::BRCOND: return LowerBRCOND(Op, DAG);
+  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
   case ISD::LOAD: {
     SDValue Result = LowerLOAD(Op, DAG);
     assert((!Result.getNode() ||

   return Chain;
 }
 
+SDValue SITargetLowering::LowerRETURNADDR(SDValue Op,
+                                                    SelectionDAG &DAG) const {
+  // Checking the depth
+  if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) {
+    DAG.getContext()->emitError(
+        "Return address can be determined only for current frame");
+    return SDValue();
+  }
+
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachineFrameInfo &MFI = MF.getFrameInfo();
+  // There is a call to @llvm.returnaddress in this function
+  MFI.setReturnAddressIsTaken(true);
+
+  const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
+  MVT VT = Op.getSimpleValueType();
+  // Get the return address reg and mark it as an implicit live-in
+  unsigned Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT));
+
+  return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
+}
+
 SDValue SITargetLowering::getFPExtOrFPTrunc(SelectionDAG &DAG,
                                             SDValue Op,
                                             const SDLoc &DL,

test/CodeGen/AMDGPU/returnaddress.ll

+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}func1
+; GCN: v_mov_b32_e32 v0, s30
+; GCN: v_mov_b32_e32 v1, s31
+; GCN: s_setpc_b64 s[30:31]
+define i8* @func1() nounwind {
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @func2() nounwind {
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 1)
+  ret i8* %0
+}