[ARM] Remove EarlyCSE from backend

[samparker]

Summary

There is an issue with early CSE hitting an assert, so temporarily remove the pass from the Arm backend.
Bug: https://bugs.llvm.org/show_bug.cgi?id=41081

[mstorsjo]

Sounds ok to me

llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp

if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
     addPass(createCFGSimplificationPass(
         1, false, false, true, true, [this](const Function &F) {
           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
         }));
 
   TargetPassConfig::addIRPasses();
 
-  // Run the parallel DSP pass and its helpers.
-  if (getOptLevel() == CodeGenOpt::Aggressive) {
-    addPass(createEarlyCSEPass());
+  // Run the parallel DSP pass.
+  if (getOptLevel() == CodeGenOpt::Aggressive) 
     addPass(createARMParallelDSPPass());
-  }
 
   // Match interleaved memory accesses to ldN/stN intrinsics.
   if (TM->getOptLevel() != CodeGenOpt::None)
     addPass(createInterleavedAccessPass());
 }
 
 void ARMPassConfig::addCodeGenPrepare() {
   if (getOptLevel() != CodeGenOpt::None)

llvm/trunk/test/CodeGen/ARM/O3-pipeline.ll

 ; CHECK:      Branch Probability Analysis
 ; CHECK:      Block Frequency Analysis
 ; CHECK:      Constant Hoisting
 ; CHECK:      Partially inline calls to library functions
 ; CHECK:      Instrument function entry/exit with calls to e.g. mcount() (post inlining)
 ; CHECK:      Scalarize Masked Memory Intrinsics
 ; CHECK:      Expand reduction intrinsics
 ; CHECK:      Dominator Tree Construction
-; CHECK:      Early CSE
 ; CHECK:      Natural Loop Information
 ; CHECK:      Scalar Evolution Analysis
 ; CHECK:      Basic Alias Analysis (stateless AA impl)
 ; CHECK:      Function Alias Analysis Results
 ; CHECK:      Loop Pass Manager
 ; CHECK:        Transform loops to use DSP intrinsics
 ; CHECK:      Interleaved Access Pass
 ; CHECK:      ARM IR optimizations

llvm/trunk/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll

entry:
   %mul.us.i118.2.i = mul i32 %inc11.us.i.1.i, %N
   %inc11.us.i.2.i = or i32 %idx, 3
   %arrayidx.us.i117.3.i = getelementptr inbounds i32, i32* %res, i32 %inc11.us.i.2.i
   store i32 0, i32* %arrayidx.us.i117.3.i, align 4
   %mul.us.i118.3.i = mul i32 %inc11.us.i.2.i, %N
   %inc11.us.i.3.i = add i32 %idx, 4
   br label %for.body
 
+; TODO: CSE, or something similar, is required to remove the duplicate loads.
 ; CHECK: %for.body
 ; CHECK: smlad
 ; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
+; CHECK-NOT: smlad r{{.*}}
 
 for.body:
   %A3 = phi i32 [ %add9.us.i.3361.i, %for.body ], [ 0, %entry ]
   %j.026.us.i.i = phi i32 [ %inc.us.i.3362.i, %for.body ], [ 0, %entry ]
   %A4 = phi i32 [ %add9.us.i.1.3.i, %for.body ], [ 0, %entry ]
   %A5 = phi i32 [ %add9.us.i.2.3.i, %for.body ], [ 0, %entry ]
   %A6 = phi i32 [ %add9.us.i.3.3.i, %for.body ], [ 0, %entry ]
   %niter335.i = phi i32 [ %niter335.nsub.3.i, %for.body ], [ %unroll_iter310.i, %entry ]

llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll

 @.str1184 = external constant [7 x i8], align 4   ; <[7 x i8]*> [#uses=0]
 @.str1285 = external constant [16 x i8], align 4  ; <[16 x i8]*> [#uses=0]
 @.str1386 = external constant [12 x i8], align 4  ; <[12 x i8]*> [#uses=0]
 @.str1487 = external constant [5 x i8], align 4   ; <[5 x i8]*> [#uses=0]
 @llvm.used = external global [1 x i8*]            ; <[1 x i8*]*> [#uses=0]
 
 define fastcc i32 @parse_percent_token() nounwind {
 entry:
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
 ; Do not convert into single stream code. BranchProbability Analysis assumes
 ; that branches which goes to "ret" instruction have lower probabilities.
   switch i32 undef, label %bb7 [
     i32 37, label %bb43
     i32 48, label %bb5
     i32 50, label %bb4
     i32 60, label %bb2
     i32 61, label %bb6