[ARC] Add more load/store variants and simple pass to generate postincrement instructions

[dantrushin]

Summary

On ARC ISA, general format of load instruction is this:

    LD<zz><.x><.aa><.di> a, [b,c]
And general format of store is this:
    ST<zz><.aa><.di> c, [b,s9]

Where:

  
<zz> is data size field and can be one of
  <empty> (bits 00) - Word (32-bit), default behavior
  B             (bits 01) - Byte
  H             (bits 10) - Half-word (16-bit)
  
 <.x> is data extend mode:
  <empty> (bit 0) - If size is not Word(32-bit), then data is zero extended
  X             (bit 1) - If size is not Word(32-bit), then data is sign extended
  
 <.aa> is address write-back mode:
  <empty> (bits 00) - no write-back
  .AW     (bits 01) - Preincrement, base register is updated pre memory transaction
  .AB      (bits 10) - Postincrement, base register is updated post memory transaction
  
 <.di> is cache bypass mode:
  <empty> (bit 0) - Cached memory access, default mode
  .DI           (bit 1) - Non-cached data memory access
  
  This patch adds these load/store instruction variants to the ARC backend and also
  adds simple pass to generate postincrement load/store instructions

[dantrushin]

llvm/lib/Target/ARC/ARCFrameLowering.cpp

297 ↗

(On Diff #189341)

Update to match instruction format change - first operand now is loaded value, not updated base address
I think this looks more natural

llvm/lib/Target/ARC/ARCInstrInfo.td

815 ↗

(On Diff #189341)

Loaded value is operand 0 now; Was 1

[petecoup]

Can you add a few disassembler tests for the new variants here?

llvm/lib/Target/ARC/ARCOptAddrMode.cpp

140 ↗

(On Diff #189341)

Other backends seem to use MRI for MachineRegisterInfo, I'd reuse that here too.

272 ↗

(On Diff #189341)

Drop braces in single-statement blocks?

339 ↗

(On Diff #189341)

Drop braces.

383 ↗

(On Diff #189341)

Typo: fit

384 ↗

(On Diff #189341)

Drop braces.

[dantrushin]

• Removed redundant braces
• Renamed RINFO parameter to more common MRI name
• Added a handful of disassembler tests

[yakush]

llvm/lib/Target/ARC/ARCOptAddrMode.cpp

10 ↗

(On Diff #189509)

add comment that pass is function level (requires Global ISEL)?
otherwise for BB-level ISel getPostIndexedAddressParts would be enough.

431 ↗

(On Diff #189509)

add TODO: to use alias here?

[petecoup]

Yes, this looks fine with me too Denis. As a process matter, perhaps it makes sense to split into 2 pieces: "Just add the instruction encodings + disasm tests", and then "add the pass to generate pre-/post-increment instructions + tests"
Both pieces look fine with me.

[dantrushin]

I do not have commit access. Pete, could you push it for me?

[petecoup]

Yes Denis, I will try to push this for you tomorrow. Thanks!

llvm/trunk/lib/Target/ARC/ARCInstrFormats.td

def MEMrlimm : Operand<iAny> {
   let PrintMethod = "printMemOperandRI";
   let DecoderMethod = "DecodeMEMrlimm";
 }
 
 def GPR32Reduced : Operand<iAny> {
   let DecoderMethod = "DecodeGBR32ShortRegister";
 }
 
+// Helper classes for load/store instructions
+class DataSizeMode<bits<2> mode, string instSfx, string asmSfx> {
+  bits<2> Value = mode;
+  string  InstSuffix = instSfx;
+  string  AsmSuffix  = asmSfx;
+}
+class ExtMode<bit mode, string instSfx, string asmSfx> {
+  bit     Value = mode;
+  string  InstSuffix = instSfx;
+  string  AsmSuffix  = asmSfx;
+}
+
+class AddrMode<bits<2> mode, string instSfx, string asmSfx> {
+  bits<2> Value = mode;
+  string  InstSuffix = instSfx;
+  string  AsmSuffix  = asmSfx;
+}
+
+class CacheMode<bit mode, string instSfx, string asmSfx> {
+  bit     Value = mode;
+  string  InstSuffix = instSfx;
+  string  AsmSuffix  = asmSfx;
+}
+
+def ByteSM : DataSizeMode<0b01, "B", "b">;
+def HalfSM : DataSizeMode<0b10, "H", "h">;
+def WordSM : DataSizeMode<0b00,  "",  "">;
+
+def NoEM      : ExtMode<0,   "",   "">;
+def SignedEM  : ExtMode<1, "_X", ".x">;
+
+def NoAM      : AddrMode<0b00, "", "">;
+def PreIncAM  : AddrMode<0b01, "_AW", ".aw">;
+def PostIncAM : AddrMode<0b10, "_AB", ".ab">;
+
+def NoCC       : CacheMode<0b0,    "",    "">;
+def UncachedCC : CacheMode<0b1, "_DI", ".di">;
+
 class InstARC<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
     : Instruction, Encoding64 {
 
   let Namespace = "ARC";
   dag OutOperandList = outs;
   dag InOperandList = ins;
   let AsmString = asmstr;
   let Pattern = pattern;
   let Size = sz;
+
+  // Load/Store instruction properties
+  DataSizeMode ZZ = WordSM;
+  ExtMode X = NoEM;
+  AddrMode AA = NoAM;
+  CacheMode DI = NoCC;
+
+  // Field used for relation models
+  string BaseOpcode = "";
+
+  //TSFlags
+  let TSFlags{1-0} = AA.Value;
 }
 
 // ARC pseudo instructions format
 class PseudoInstARC<dag outs, dag ins, string asmstr, list<dag> pattern>
    : InstARC<0, outs, ins, asmstr, pattern> {
   let isPseudo = 1;
 }
 
class F32_LD_RS9<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
   let Inst{23-16} = S9{7-0};
   let Inst{15} = S9{8};
   let Inst{14-12} = B{5-3};
   let Inst{11} = di;
   let Inst{10-9} = aa;
   let Inst{8-7} = zz;
   let Inst{6} = x;
   let Inst{5-0} = A;
+
+  let BaseOpcode = "ld_rs9";
 }
 
 class F32_LD_ADDR<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
                   string asmstr, list<dag> pattern> :
   F32_LD_RS9<x, aa, di, zz, outs, ins, asmstr, pattern> {
   bits<15> addr;
 
   let B = addr{14-9};
   let S9 = addr{8-0};
+
+  let BaseOpcode = "ld_rs9";
 }
 
 
 // LImm Load.  The 32-bit immediate address is in Inst[63-32].
 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
 // | 1| 1| 0| 0                        | 1| 1| 1|di| 0|0|zz |x|A          |
 class F32_LD_LIMM<bit x, bit di, bits<2> zz, dag outs, dag ins,
                   string asmstr, list<dag> pattern> :
   InstARC<8, outs, ins, asmstr, pattern> {
   bits<6> LImmReg = 0b111110;
   bits<6> A;
   bits<32> LImm;
 
   let Inst{63-32} = LImm;
   let Inst{31-27} = 0b00010;
   let Inst{26-24} = LImmReg{2-0};
   let Inst{23-15} = 0;
   let Inst{14-12} = LImmReg{5-3};
   let Inst{11} = di;
   let Inst{10-9} = 0;
   let Inst{8-7} = zz;
   let Inst{6} = x;
   let Inst{5-0} = A;
   let DecoderMethod = "DecodeLdLImmInstruction";
+
+  let BaseOpcode = "ld_limm";
 }
 
 // Register + LImm load.  The 32-bit immediate address is in Inst[63-32].
 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
 // |B[2-0]  |aa   | 1| 1| 0|zz   | x|di|B[5-3]  | 1| 1|1|1|1|0|A          |
 class F32_LD_RLIMM<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
                    string asmstr, list<dag> pattern> :
   InstARC<8, outs, ins, asmstr, pattern> {
class F32_LD_RLIMM<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
   let Inst{21-19} = 0b110;
   let Inst{18-17} = zz;
   let Inst{16} = x;
   let Inst{15} = di;
   let Inst{14-12} = B{5-3};
   let Inst{11-6} = LImmReg;
   let Inst{5-0} = A;
   let DecoderMethod = "DecodeLdRLImmInstruction";
+
+  let BaseOpcode = "ld_rlimm";
 }
 
 // Register + S9 Store. (B + S9)
 // |26|25|24|23|22|21|20|19|18|17|16|15   |14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
 // |B[2-0]  |S9[7-0]                |S9[8]|B[5-3]  |C            |di|aa |zz |0|
 class F32_ST_RS9<bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
                  string asmstr, list<dag> pattern> :
   InstARC<4, outs, ins, asmstr, pattern> {
   bits<6> B;
   bits<6> C;
   bits<9> S9;
 
   let Inst{31-27} = 0b00011;
   let Inst{26-24} = B{2-0};
   let Inst{23-16} = S9{7-0};
   let Inst{15} = S9{8};
   let Inst{14-12} = B{5-3};
   let Inst{11-6} = C;
   let Inst{5} = di;
   let Inst{4-3} = aa;
   let Inst{2-1} = zz;
   let Inst{0} = 0;
+
+  let BaseOpcode = "st_rs9";
 }
 
 class F32_ST_ADDR<bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
                   string asmstr, list<dag> pattern> :
   F32_ST_RS9<aa, di, zz, outs, ins, asmstr, pattern> {
   bits<15> addr;
 
   let B = addr{14-9};
   let S9 = addr{8-0};
+
+  let BaseOpcode = "st_rs9";
 }
 
 // LImm Store.
 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
 // | 1| 1| 0| 0                        | 1| 1| 1|C            |di|0|0|zz |0|
 class F32_ST_LIMM<bit di, bits<2> zz, dag outs, dag ins,
                   string asmstr, list<dag> pattern> :
   InstARC<8, outs, ins, asmstr, pattern> {
   bits<6> LImmReg = 0b111110;
   bits<6> C;
   bits<32> LImm;
 
   let Inst{63-32} = LImm;
   let Inst{31-27} = 0b00011;
   let Inst{26-24} = LImmReg{2-0};
   let Inst{23-15} = 0;
   let Inst{14-12} = LImmReg{5-3};
   let Inst{11-6} = C;
   let Inst{5} = di;
   let Inst{4-3} = 0;
   let Inst{2-1} = zz;
   let Inst{0} = 0;
   let DecoderMethod = "DecodeStLImmInstruction";
+
+  let BaseOpcode = "st_limm";
 }
 
 // Compact Move/Load.
 // |10|9|8|7|6|5|4|3|2|1|0|
 // |      |h    |   |i|H  |
 class F16_COMPACT<bits<1> i, dag outs, dag ins,
                  string asmstr> :
   InstARC<2, outs, ins, asmstr, []> {

llvm/trunk/lib/Target/ARC/ARCInstrInfo.h

public:
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI, unsigned DestReg,
                             int FrameIndex, const TargetRegisterClass *RC,
                             const TargetRegisterInfo *TRI) const override;
 
   bool
   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
+
+  bool isPostIncrement(const MachineInstr &MI) const override;
+
+  // ARC-specific
+  bool isPreIncrement(const MachineInstr &MI) const;
+
+  virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
+                                        unsigned &BasePos,
+                                        unsigned &OffsetPos) const override;
+
   // Emit code before MBBI to load immediate value into physical register Reg.
   // Returns an iterator to the new instruction.
   MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB,
                                             MachineBasicBlock::iterator MI,
                                             unsigned Reg, uint64_t Value) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H

llvm/trunk/lib/Target/ARC/ARCInstrInfo.cpp

 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_CTOR_DTOR
 #include "ARCGenInstrInfo.inc"
 
 #define DEBUG_TYPE "arc-inst-info"
+
+enum AddrIncType {
+    NoAddInc = 0,
+    PreInc   = 1,
+    PostInc  = 2,
+    Scaled   = 3
+};
+
+enum TSFlagsConstants {
+    TSF_AddrModeOff = 0,
+    TSF_AddModeMask = 3
+};
+
 // Pin the vtable to this file.
 void ARCInstrInfo::anchor() {}
 
 ARCInstrInfo::ARCInstrInfo()
     : ARCGenInstrInfo(ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI() {}
 
 static bool isZeroImm(const MachineOperand &Op) {
   return Op.isImm() && Op.getImm() == 0;

 unsigned ARCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   if (MI.isInlineAsm()) {
     const MachineFunction *MF = MI.getParent()->getParent();
     const char *AsmStr = MI.getOperand(0).getSymbolName();
     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
   }
   return MI.getDesc().getSize();
 }
+
+bool ARCInstrInfo::isPostIncrement(const MachineInstr &MI) const {
+  const MCInstrDesc &MID = MI.getDesc();
+  const uint64_t F = MID.TSFlags;
+  return ((F >> TSF_AddrModeOff) & TSF_AddModeMask) == PostInc;
+}
+
+bool ARCInstrInfo::isPreIncrement(const MachineInstr &MI) const {
+  const MCInstrDesc &MID = MI.getDesc();
+  const uint64_t F = MID.TSFlags;
+  return ((F >> TSF_AddrModeOff) & TSF_AddModeMask) == PreInc;
+}
+
+bool ARCInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
+                                        unsigned &BasePos,
+                                        unsigned &OffsetPos) const {
+  if (!MI.mayLoad() && !MI.mayStore())
+    return false;
+
+  BasePos = 1;
+  OffsetPos = 2;
+
+  if (isPostIncrement(MI) || isPreIncrement(MI)) {
+    BasePos++;
+    OffsetPos++;
+  }
+
+  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
+    return false;
+
+  return true;
+}

llvm/trunk/lib/Target/ARC/ARCInstrInfo.td

let isBarrier = 1 in {
     def GEN_J_S_D_BLINK : F16_GEN_ZOP<0x7, "j_s.d\t[%blink]">;
   } // let isBarrier
 } // let isReturn, isTerminator
 
 //----------------------------------------------------------------------------
 // Load/Store instructions.
 //----------------------------------------------------------------------------
 
+// Filter  class for load/store mappings
+class ArcLdStRel;
+
 // Load instruction variants:
 // Control bits: x, aa, di, zz
 // x - sign extend.
 // aa - incrementing mode. (N/A for LIMM).
 // di - uncached.
 // zz - data size.
-multiclass ArcLdInst<bits<2> zz, string asmop> {
-  let mayLoad = 1 in {
-  def _rs9 : F32_LD_ADDR<0, 0b00, 0, zz,
-                         (outs GPR32:$A), (ins MEMrs9:$addr),
-                         !strconcat(asmop, "\t$A, [$addr]"), []>;
-
-  def _limm : F32_LD_LIMM<0, 0, zz,
-                         (outs GPR32:$A), (ins MEMii:$addr),
-                         !strconcat(asmop, "\t$A, [$addr]"), []>;
-
-  def _rlimm : F32_LD_RLIMM<0, 0b00, 0, zz,
-                           (outs GPR32:$A), (ins MEMrlimm:$addr),
-                           !strconcat(asmop, "\t$A, [$addr]"), []>;
-
-  def _X_rs9 : F32_LD_ADDR<1, 0b00, 0, zz,
-                         (outs GPR32:$A), (ins MEMrs9:$addr),
-                         !strconcat(asmop, ".x\t$A, [$addr]"), []>;
+multiclass ArcLdInst<DataSizeMode zz, ExtMode x, CacheMode di, string asmop> {
+  let mayLoad = 1, ZZ = zz, X = x, DI = di in {
+    def _rs9: F32_LD_ADDR<x.Value, NoAM.Value, di.Value, zz.Value,
+         (outs GPR32:$A), (ins MEMrs9:$addr),
+         !strconcat(asmop, "\t$A, [$addr]"), []>, ArcLdStRel;
 
-  def _X_limm : F32_LD_LIMM<1, 0, zz,
-                         (outs GPR32:$A), (ins MEMii:$addr),
-                         !strconcat(asmop, ".x\t$A, [$addr]"), []>;
+    def _limm: F32_LD_LIMM<x.Value, di.Value, zz.Value,
+         (outs GPR32:$A), (ins MEMii:$addr),
+         !strconcat(asmop, "\t$A, [$addr]"), []>, ArcLdStRel;
 
-  def _X_rlimm : F32_LD_RLIMM<1, 0b00, 0, zz,
-                           (outs GPR32:$A), (ins MEMrlimm:$addr),
-                           !strconcat(asmop, ".x\t$A, [$addr]"), []>;
+    def _rlimm: F32_LD_RLIMM<x.Value, NoAM.Value, di.Value, zz.Value,
+           (outs GPR32:$A), (ins MEMrlimm:$addr),
+           !strconcat(asmop, "\t$A, [$addr]"), []>, ArcLdStRel;
 
-  def _AB_rs9 : F32_LD_RS9<0, 0b10, 0, zz,
-                      (outs GPR32:$addrout, GPR32:$A),
-                      (ins GPR32:$B, immS<9>:$S9),
-                      !strconcat(asmop, ".ab\t$A, [$B,$S9]"), []>
-    { let Constraints = "$addrout = $B"; }
+    foreach aa = [PreIncAM, PostIncAM] in {
+      def aa.InstSuffix#_rs9: F32_LD_RS9<x.Value, aa.Value, di.Value, zz.Value,
+            (outs GPR32:$A, GPR32:$addrout),
+            (ins GPR32:$B, immS<9>:$S9),
+            asmop#aa.AsmSuffix#"\t$A, [$B,$S9]", []>, ArcLdStRel
+             { let Constraints = "$addrout = $B"; let AA = aa; }
+    }
   }
 }
-                         
-// Load instruction definitions.
-defm LD  : ArcLdInst<0b00, "ld">;
-defm LDH : ArcLdInst<0b10, "ldh">;
-defm LDB : ArcLdInst<0b01, "ldb">;
+foreach di = [NoCC, UncachedCC] in {
+  defm LD#di.InstSuffix : ArcLdInst<WordSM, NoEM, di, "ld"#di.AsmSuffix>;
+  foreach zz = [ByteSM, HalfSM] in {
+    foreach x = [NoEM, SignedEM] in {
+      defm LD#zz.InstSuffix#x.InstSuffix#di.InstSuffix : ArcLdInst<zz, x, di, "ld"#zz.AsmSuffix#x.AsmSuffix#di.AsmSuffix>;
+    }
+  }
+}
 
 // Load instruction patterns.
 // 32-bit loads.
 def : Pat<(load AddrModeS9:$addr), (LD_rs9 AddrModeS9:$addr)>;
 def : Pat<(load AddrModeImm:$addr), (LD_limm AddrModeImm:$addr)>;
 def : Pat<(load AddrModeFar:$addr), (LD_rs9 AddrModeFar:$addr)>;
 
 // 16-bit loads

 def : Pat<(sextloadi8 AddrModeS9:$addr),(LDB_X_rs9 AddrModeS9:$addr)>;
 
 
 // Store instruction variants:
 // Control bits: aa, di, zz
 // aa - incrementing mode. (N/A for LIMM).
 // di - uncached.
 // zz - data size.
-multiclass ArcStInst<bits<2> zz, string asmop> {
-  let mayStore = 1 in {
-  def _rs9  : F32_ST_ADDR<0b00, 0, zz, (outs), (ins GPR32:$C, MEMrs9:$addr),
-                         !strconcat(asmop, "\t$C, [$addr]"), []>;
+multiclass ArcStInst<DataSizeMode zz, CacheMode di, string asmop> {
+  let mayStore = 1, ZZ = zz, DI = di in {
+    def _rs9: F32_ST_ADDR<NoAM.Value, di.Value, zz.Value,
+         (outs), (ins GPR32:$C, MEMrs9:$addr),
+         !strconcat(asmop, "\t$C, [$addr]"), []>, ArcLdStRel;
+
+    def _limm: F32_ST_LIMM<di.Value, zz.Value,
+         (outs), (ins GPR32:$C, MEMii:$addr),
+         !strconcat(asmop, "\t$C, [$addr]"), []>, ArcLdStRel;
 
-  def _limm : F32_ST_LIMM<0, zz, (outs), (ins GPR32:$C, MEMii:$addr),
-                         !strconcat(asmop, "\t$C, [$addr]"), []>;
 
-  def _AW_rs9 : F32_ST_RS9<0b01, 0, zz, (outs GPR32:$addrout),
-                      (ins GPR32:$C, GPR32:$B, immS<9>:$S9),
-                      !strconcat(asmop, ".aw\t$C, [$B,$S9]"), []>
-    { let Constraints = "$addrout = $B"; }
+    foreach aa = [PreIncAM, PostIncAM] in {
+      def aa.InstSuffix#_rs9: F32_ST_RS9<aa.Value, di.Value, zz.Value,
+            (outs GPR32:$addrout),
+            (ins GPR32:$C, GPR32:$B, immS<9>:$S9),
+            asmop#aa.AsmSuffix#"\t$C, [$B,$S9]", []>, ArcLdStRel
+             { let Constraints = "$addrout = $B"; let AA = aa; }
+    }
   }
 }
 
-// Store instruction definitions.
-defm ST  : ArcStInst<0b00, "st">;
-defm STH : ArcStInst<0b10, "sth">;
-defm STB : ArcStInst<0b01, "stb">;
+foreach di = [NoCC, UncachedCC] in {
+  foreach zz = [ByteSM, HalfSM, WordSM] in {
+      defm ST#zz.InstSuffix#di.InstSuffix : ArcStInst<zz, di, "st"#zz.AsmSuffix#di.AsmSuffix>;
+  }
+}
 
 // Store instruction patterns.
 // 32-bit stores
 def : Pat<(store i32:$C, AddrModeS9:$addr),
           (ST_rs9 i32:$C, AddrModeS9:$addr)>;
 def : Pat<(store i32:$C, AddrModeImm:$addr),
           (ST_limm i32:$C, AddrModeImm:$addr)>;
 
 // 16-bit stores
 def : Pat<(truncstorei16 i32:$C, AddrModeS9:$addr),
           (STH_rs9 i32:$C, AddrModeS9:$addr)>;
 def : Pat<(truncstorei16 i32:$C, AddrModeImm:$addr),
           (STH_limm i32:$C, AddrModeImm:$addr)>;
 
 // 8-bit stores
 def : Pat<(truncstorei8 i32:$C, AddrModeS9:$addr),
           (STB_rs9 i32:$C, AddrModeS9:$addr)>;
 def : Pat<(truncstorei8 i32:$C, AddrModeImm:$addr),
           (STB_limm i32:$C, AddrModeImm:$addr)>;
 
+def getPostIncOpcode : InstrMapping {
+  let FilterClass = "ArcLdStRel";
+  let RowFields = [ "BaseOpcode", "ZZ", "DI", "X"];
+  let ColFields = [ "AA" ];
+  let KeyCol = [ "NoAM" ];
+  let ValueCols = [["PostIncAM"]];
+}

llvm/trunk/test/MC/Disassembler/ARC/ldst.txt

 0x00 0x16 0x06 0x70 0x00 0x00 0xb0 0xf9
 
 # CHECK: stb %r2, [%sp,35]
 0x23 0x1c 0x82 0x30
 
 # CHECK: st %r7, [63920]
 0x00 0x1e 0xc0 0x71 0x00 0x00 0xb0 0xf9
 
+# CHECK: ldb.ab %r1, [%r0,1]
+0x01 0x10 0x81 0x04
+
+# CHECK: stb.ab %r2, [%r0,1]
+0x01 0x18 0x92 0x00
+
+# CHECK: ldh.ab  %r3, [%r0,12]
+0x0C 0x10 0x03 0x05
+
+# CHECK: sth.ab  %r4, [%r0,18]
+0x12 0x18 0x14 0x01
+
+# CHECK: ld.ab   %r5, [%r2,128]
+0x80 0x12 0x05 0x04
+
+# CHECK: st.ab   %r6, [%r2,64]
+0x40 0x1A 0x90 0x01
+
+# CHECK: ldb.aw %r7, [%r0,1]
+0x01 0x10 0x87 0x02
+
+# CHECK: stb.aw %r8, [%r0,1]
+0x01 0x18 0x0A 0x02
+
+# CHECK: ldh.aw  %r3, [%r0,12]
+0x0C 0x10 0x03 0x03
+
+# CHECK: sth.aw  %r3, [%r0,18]
+0x12 0x18 0xCC 0x00
+
+# CHECK: ld.aw   %r6, [%r2,128]
+0x80 0x12 0x06 0x02
+
+# CHECK: st.aw   %r6, [%r2,64]
+0x40 0x1A 0x88 0x01
+
+# CHECK: ld.aw   %r6, [%r2,128]
+0x80 0x12 0x06 0x02
+
+# CHECK: st.aw   %r6, [%r2,64]
+0x40 0x1A 0x88 0x01
+
+# CHECK: ldb.x.di.aw %r0, [%r8,8]
+0x08 0x10 0xC0 0x1A
+
+# CHECK: stb.di.ab   %r0, [%r9,64]
+0x40 0x19 0x32 0x10