This is an archive of the discontinued LLVM Phabricator instance.

[ARC] Add more load/store variants and simple pass to generate postincrement instructions

Authored by dantrushin on Mar 5 2019, 10:10 AM.
"Like" token, awarded by yakush.



On ARC ISA, general format of load instruction is this:

    LD<zz><.x><.aa><.di> a, [b,c]
And general format of store is this:
    ST<zz><.aa><.di> c, [b,s9]


<zz> is data size field and can be one of
  <empty> (bits 00) - Word (32-bit), default behavior
  B             (bits 01) - Byte
  H             (bits 10) - Half-word (16-bit)
 <.x> is data extend mode:
  <empty> (bit 0) - If size is not Word(32-bit), then data is zero extended
  X             (bit 1) - If size is not Word(32-bit), then data is sign extended
 <.aa> is address write-back mode:
  <empty> (bits 00) - no write-back
  .AW     (bits 01) - Preincrement, base register is updated pre memory transaction
  .AB      (bits 10) - Postincrement, base register is updated post memory transaction
 <.di> is cache bypass mode:
  <empty> (bit 0) - Cached memory access, default mode
  .DI           (bit 1) - Non-cached data memory access
  This patch adds these load/store instruction variants to the ARC backend and also
  adds simple pass to generate postincrement load/store instructions

Diff Detail


Event Timeline

dantrushin created this revision.Mar 5 2019, 10:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 5 2019, 10:10 AM
dantrushin marked an inline comment as done.Mar 5 2019, 10:17 AM
dantrushin added inline comments.
297 ↗(On Diff #189341)

Update to match instruction format change - first operand now is loaded value, not updated base address
I think this looks more natural

815 ↗(On Diff #189341)

Loaded value is operand 0 now; Was 1

Can you add a few disassembler tests for the new variants here?

140 ↗(On Diff #189341)

Other backends seem to use MRI for MachineRegisterInfo, I'd reuse that here too.

272 ↗(On Diff #189341)

Drop braces in single-statement blocks?

339 ↗(On Diff #189341)

Drop braces.

383 ↗(On Diff #189341)

Typo: fit

384 ↗(On Diff #189341)

Drop braces.

dantrushin updated this revision to Diff 189509.Mar 6 2019, 7:20 AM
  • Removed redundant braces
  • Renamed RINFO parameter to more common MRI name
  • Added a handful of disassembler tests
yakush awarded a token.Mar 7 2019, 6:57 AM
yakush added a subscriber: yakush.
yakush accepted this revision.Mar 7 2019, 7:05 AM
yakush added inline comments.
10 ↗(On Diff #189509)

add comment that pass is function level (requires Global ISEL)?
otherwise for BB-level ISel getPostIndexedAddressParts would be enough.

431 ↗(On Diff #189509)

add TODO: to use alias here?

This revision is now accepted and ready to land.Mar 7 2019, 7:05 AM
petecoup accepted this revision.Mar 7 2019, 8:14 AM

Yes, this looks fine with me too Denis. As a process matter, perhaps it makes sense to split into 2 pieces: "Just add the instruction encodings + disasm tests", and then "add the pass to generate pre-/post-increment instructions + tests"
Both pieces look fine with me.

I do not have commit access. Pete, could you push it for me?

Yes Denis, I will try to push this for you tomorrow. Thanks!

This revision was automatically updated to reflect the committed changes.