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Differential D58561

[AArch64] Generate FP16 vector compare instructions
ClosedPublic

Authored by az on Feb 22 2019, 4:27 PM.

Details

Reviewers
SjoerdMeijer
Summary

We currently generate inefficient code for fp16 vector compare instructions: Comparison is done one element at a time. With this patch and when the fp16 feature is on, vector comparison instructions are generated.

Diff Detail

Event Timeline

az created this revision.Feb 22 2019, 4:27 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 22 2019, 4:27 PM
Herald added subscribers: llvm-commits, jdoerfert, hiraditya and 2 others. · View Herald Transcript
SjoerdMeijer accepted this revision.Feb 25 2019, 1:00 AM

LGTM, with one nit inline.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
7793

Just looking at this if we can simplify this if-else and asserts. Folding the FullFP16 into the assert is probably not going to make things much clearer. I guess this is covering it:

assert(( !FullFP16 && LHS.getValueType().getVectorElementType() != MVT::f16)  || 
             LHS.getValueType().getVectorElementType() != MVT::f128);
This revision is now accepted and ready to land.Feb 25 2019, 1:00 AM
SjoerdMeijer closed this revision.Mar 5 2019, 12:56 AM

Committed in rL355050

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
13 lines
test/
CodeGen/
AArch64/
144 lines
130 lines

Diff 188007

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,773 Lines • ▼ Show 20 Lines if (LHS.getValueType().getVectorElementType().isInteger()) {
return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType()); return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
} }
const bool FullFP16 = const bool FullFP16 =
static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16(); static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
// Make v4f16 (only) fcmp operations utilise vector instructions // Make v4f16 (only) fcmp operations utilise vector instructions
// v8f16 support will be a litle more complicated // v8f16 support will be a litle more complicated
if (LHS.getValueType().getVectorElementType() == MVT::f16) { if (!FullFP16 && LHS.getValueType().getVectorElementType() == MVT::f16) {
if (!FullFP16 && LHS.getValueType().getVectorNumElements() == 4) { if (LHS.getValueType().getVectorNumElements() == 4) {
LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, LHS); LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, LHS);
RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, RHS); RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, RHS);
SDValue NewSetcc = DAG.getSetCC(dl, MVT::v4i16, LHS, RHS, CC); SDValue NewSetcc = DAG.getSetCC(dl, MVT::v4i16, LHS, RHS, CC);
DAG.ReplaceAllUsesWith(Op, NewSetcc); DAG.ReplaceAllUsesWith(Op, NewSetcc);
CmpVT = MVT::v4i32; CmpVT = MVT::v4i32;
} else } else
return SDValue(); return SDValue();
} }
if (FullFP16)
SjoerdMeijerUnsubmitted
Not Done
ReplyInline Actions

Just looking at this if we can simplify this if-else and asserts. Folding the FullFP16 into the assert is probably not going to make things much clearer. I guess this is covering it:

assert(( !FullFP16 && LHS.getValueType().getVectorElementType() != MVT::f16)  || 
             LHS.getValueType().getVectorElementType() != MVT::f128);
SjoerdMeijer: Just looking at this if we can simplify this if-else and asserts. Folding the FullFP16 into the…
assert(LHS.getValueType().getVectorElementType() == MVT::f16 ||
LHS.getValueType().getVectorElementType() == MVT::f32 ||
LHS.getValueType().getVectorElementType() == MVT::f64);
else
assert(LHS.getValueType().getVectorElementType() == MVT::f32 || assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
LHS.getValueType().getVectorElementType() == MVT::f64); LHS.getValueType().getVectorElementType() == MVT::f64);
// Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
// clean. Some of them require two branches to implement. // clean. Some of them require two branches to implement.
AArch64CC::CondCode CC1, CC2; AArch64CC::CondCode CC1, CC2;
bool ShouldInvert; bool ShouldInvert;
changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert); changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath; bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
▲ Show 20 Lines • Show All 4,146 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll

Show First 20 Lines • Show All 298 Lines • ▼ Show 20 Lines
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmeq ; CHECK-CVT: fcmeq
; CHECK-CVT: mvn ; CHECK-CVT: mvn
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_une: ; CHECK-FP16-LABEL: test_fcmp_une:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmeq v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, ne
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, ne
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, ne
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, ne
; CHECK-FP16: ret
%1 = fcmp une <4 x half> %a, %b %1 = fcmp une <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ueq: ; CHECK-CVT-LABEL: test_fcmp_ueq:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmgt ; CHECK-CVT: fcmgt
; CHECK-CVT: fcmgt ; CHECK-CVT: fcmgt
; CHECK-CVT: orr ; CHECK-CVT: orr
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: mvn ; CHECK-CVT: mvn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_ueq: ; CHECK-FP16-LABEL: test_fcmp_ueq:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, eq ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, eq
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, eq
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, eq
; CHECK-FP16: ret
%1 = fcmp ueq <4 x half> %a, %b %1 = fcmp ueq <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ugt: ; CHECK-CVT-LABEL: test_fcmp_ugt:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmge ; CHECK-CVT: fcmge
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: mvn ; CHECK-CVT: mvn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_ugt: ; CHECK-FP16-LABEL: test_fcmp_ugt:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, hi
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, hi
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, hi
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, hi
; CHECK-FP16: ret
%1 = fcmp ugt <4 x half> %a, %b %1 = fcmp ugt <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_uge: ; CHECK-CVT-LABEL: test_fcmp_uge:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmgt ; CHECK-CVT: fcmgt
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: mvn ; CHECK-CVT: mvn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_uge: ; CHECK-FP16-LABEL: test_fcmp_uge:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, pl
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, pl
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, pl
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, pl
; CHECK-FP16: ret
%1 = fcmp uge <4 x half> %a, %b %1 = fcmp uge <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ult: ; CHECK-CVT-LABEL: test_fcmp_ult:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmge ; CHECK-CVT: fcmge
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: mvn ; CHECK-CVT: mvn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_ult: ; CHECK-FP16-LABEL: test_fcmp_ult:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, lt
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, lt
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, lt
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, lt
; CHECK-FP16: ret
%1 = fcmp ult <4 x half> %a, %b %1 = fcmp ult <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ule: ; CHECK-CVT-LABEL: test_fcmp_ule:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmgt ; CHECK-CVT: fcmgt
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: mvn ; CHECK-CVT: mvn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_ule: ; CHECK-FP16-LABEL: test_fcmp_ule:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, le
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, le
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, le
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, le
; CHECK-FP16: ret
%1 = fcmp ule <4 x half> %a, %b %1 = fcmp ule <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_uno: ; CHECK-CVT-LABEL: test_fcmp_uno:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmge ; CHECK-CVT: fcmge
; CHECK-CVT: fcmgt ; CHECK-CVT: fcmgt
; CHECK-CVT: orr ; CHECK-CVT: orr
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: mvn ; CHECK-CVT: mvn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_uno: ; CHECK-FP16-LABEL: test_fcmp_uno:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, vs ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, vs
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, vs
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, vs
; CHECK-FP16: ret
%1 = fcmp uno <4 x half> %a, %b %1 = fcmp uno <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_one: ; CHECK-CVT-LABEL: test_fcmp_one:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmgt ; CHECK-CVT: fcmgt
; CHECK-CVT: fcmgt ; CHECK-CVT: fcmgt
; CHECK-CVT: orr ; CHECK-CVT: orr
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_one: ; CHECK-FP16-LABEL: test_fcmp_one:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, mi ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, mi
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, mi
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, mi
; CHECK-FP16: ret
%1 = fcmp one <4 x half> %a, %b %1 = fcmp one <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_oeq: ; CHECK-CVT-LABEL: test_fcmp_oeq:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmeq ; CHECK-CVT: fcmeq
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_oeq: ; CHECK-FP16-LABEL: test_fcmp_oeq:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmeq v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, eq
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, eq
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, eq
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, eq
; CHECK-FP16: ret
%1 = fcmp oeq <4 x half> %a, %b %1 = fcmp oeq <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ogt: ; CHECK-CVT-LABEL: test_fcmp_ogt:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmgt ; CHECK-CVT: fcmgt
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_ogt: ; CHECK-FP16-LABEL: test_fcmp_ogt:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, gt
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, gt
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, gt
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, gt
; CHECK-FP16: ret
%1 = fcmp ogt <4 x half> %a, %b %1 = fcmp ogt <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_oge: ; CHECK-CVT-LABEL: test_fcmp_oge:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmge ; CHECK-CVT: fcmge
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_oge: ; CHECK-FP16-LABEL: test_fcmp_oge:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, ge
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, ge
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, ge
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, ge
; CHECK-FP16: ret
%1 = fcmp oge <4 x half> %a, %b %1 = fcmp oge <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_olt: ; CHECK-CVT-LABEL: test_fcmp_olt:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmgt ; CHECK-CVT: fcmgt
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_olt: ; CHECK-FP16-LABEL: test_fcmp_olt:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, mi
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, mi
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, mi
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, mi
; CHECK-FP16: ret
%1 = fcmp olt <4 x half> %a, %b %1 = fcmp olt <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ole: ; CHECK-CVT-LABEL: test_fcmp_ole:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmge ; CHECK-CVT: fcmge
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_ole: ; CHECK-FP16-LABEL: test_fcmp_ole:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, ls
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, ls
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, ls
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, ls
; CHECK-FP16: ret
%1 = fcmp ole <4 x half> %a, %b %1 = fcmp ole <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 { define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 {
; CHECK-CVT-LABEL: test_fcmp_ord: ; CHECK-CVT-LABEL: test_fcmp_ord:
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcvtl ; CHECK-CVT: fcvtl
; CHECK-CVT: fcmge ; CHECK-CVT: fcmge
; CHECK-CVT: fcmgt ; CHECK-CVT: fcmgt
; CHECK-CVT: orr ; CHECK-CVT: orr
; CHECK-CVT: xtn ; CHECK-CVT: xtn
; CHECK-CVT: ret ; CHECK-CVT: ret
; CHECK-FP16-LABEL: test_fcmp_ord: ; CHECK-FP16-LABEL: test_fcmp_ord:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16: fcmp h{{.}}, h{{.}} ; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: csetm {{.*}}, vc ; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, vc
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, vc
; CHECK-FP16: fcmp h{{.}}, h{{.}}
; CHECK-FP16: csetm {{.*}}, vc
; CHECK-FP16: ret
%1 = fcmp ord <4 x half> %a, %b %1 = fcmp ord <4 x half> %a, %b
ret <4 x i1> %1 ret <4 x i1> %1
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll

Show First 20 Lines • Show All 444 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <8 x i1> @test_fcmp_une(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_une(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_une: ; CHECK-FP16-LABEL: test_fcmp_une:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmeq v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp une <8 x half> %a, %b %1 = fcmp une <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ueq(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ueq(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_ueq: ; CHECK-FP16-LABEL: test_fcmp_ueq:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp ueq <8 x half> %a, %b %1 = fcmp ueq <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ugt(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ugt(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_ugt: ; CHECK-FP16-LABEL: test_fcmp_ugt:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp ugt <8 x half> %a, %b %1 = fcmp ugt <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_uge(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_uge(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_uge: ; CHECK-FP16-LABEL: test_fcmp_uge:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp uge <8 x half> %a, %b %1 = fcmp uge <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ult(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ult(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_ult: ; CHECK-FP16-LABEL: test_fcmp_ult:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp ult <8 x half> %a, %b %1 = fcmp ult <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ule(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ule(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_ule: ; CHECK-FP16-LABEL: test_fcmp_ule:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp ule <8 x half> %a, %b %1 = fcmp ule <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_uno(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_uno(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_uno: ; CHECK-FP16-LABEL: test_fcmp_uno:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp uno <8 x half> %a, %b %1 = fcmp uno <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_one(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_one(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_one: ; CHECK-FP16-LABEL: test_fcmp_one:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp one <8 x half> %a, %b %1 = fcmp one <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_oeq(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_oeq(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_oeq: ; CHECK-FP16-LABEL: test_fcmp_oeq:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmeq v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp oeq <8 x half> %a, %b %1 = fcmp oeq <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ogt(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ogt(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_ogt: ; CHECK-FP16-LABEL: test_fcmp_ogt:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp ogt <8 x half> %a, %b %1 = fcmp ogt <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_oge(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_oge(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_oge: ; CHECK-FP16-LABEL: test_fcmp_oge:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp oge <8 x half> %a, %b %1 = fcmp oge <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_olt(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_olt(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_olt: ; CHECK-FP16-LABEL: test_fcmp_olt:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp olt <8 x half> %a, %b %1 = fcmp olt <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ole(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ole(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_ole: ; CHECK-FP16-LABEL: test_fcmp_ole:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp ole <8 x half> %a, %b %1 = fcmp ole <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
define <8 x i1> @test_fcmp_ord(<8 x half> %a, <8 x half> %b) #0 { define <8 x i1> @test_fcmp_ord(<8 x half> %a, <8 x half> %b) #0 {
; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. ; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16.
; CHECK-FP16-LABEL: test_fcmp_ord: ; CHECK-FP16-LABEL: test_fcmp_ord:
; CHECK-FP16-NOT: fcvt ; CHECK-FP16-NOT: fcvt
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}} ; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
%1 = fcmp ord <8 x half> %a, %b %1 = fcmp ord <8 x half> %a, %b
ret <8 x i1> %1 ret <8 x i1> %1
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }