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Differential D58479

This is just a try
AbandonedPublic

Authored by cfang on Feb 20 2019, 2:28 PM.

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cfang created this revision.Feb 20 2019, 2:28 PM
Herald added subscribers: nhaehnle, wdng, jvesely, arsenm. · View Herald TranscriptFeb 20 2019, 2:28 PM
cfang abandoned this revision.Feb 20 2019, 2:34 PM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
11 lines
18 lines
test/
CodeGen/
AMDGPU/
2 lines

Diff 187677

lib/Target/AMDGPU/SIInstrInfo.cpp

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if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
return false; return false;
if (AA && MIa.hasOneMemOperand() && MIb.hasOneMemOperand()) {
const MachineMemOperand *MMOa = *MIa.memoperands_begin();
const MachineMemOperand *MMOb = *MIb.memoperands_begin();
if (MMOa->getValue() && MMOb->getValue()) {
MemoryLocation LocA(MMOa->getValue(), MMOa->getSize(), MMOa->getAAInfo());
MemoryLocation LocB(MMOb->getValue(), MMOb->getSize(), MMOb->getAAInfo());
if (!AA->alias(LocA, LocB))
return true;
}
}
// TODO: Should we check the address space from the MachineMemOperand? That // TODO: Should we check the address space from the MachineMemOperand? That
// would allow us to distinguish objects we know don't alias based on the // would allow us to distinguish objects we know don't alias based on the
// underlying address space, even if it was lowered to a different one, // underlying address space, even if it was lowered to a different one,
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lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

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static bool memAccessesCanBeReordered(MachineBasicBlock::iterator A, static bool memAccessesCanBeReordered(MachineBasicBlock::iterator A,
MachineBasicBlock::iterator B, MachineBasicBlock::iterator B,
const SIInstrInfo *TII,
AliasAnalysis *AA) { AliasAnalysis *AA) {
// RAW or WAR - cannot reorder // RAW or WAR - cannot reorder
// WAW - cannot reorder // WAW - cannot reorder
// RAR - safe to reorder // RAR - safe to reorder
return !(A->mayStore() || B->mayStore()) || return !(A->mayStore() || B->mayStore()) || !A->mayAlias(AA, *B, true);
TII->areMemAccessesTriviallyDisjoint(*A, *B, AA);
} }
// Add MI and its defs to the lists if MI reads one of the defs that are // Add MI and its defs to the lists if MI reads one of the defs that are
Context not available.
static bool canMoveInstsAcrossMemOp(MachineInstr &MemOp, static bool canMoveInstsAcrossMemOp(MachineInstr &MemOp,
ArrayRef<MachineInstr *> InstsToMove, ArrayRef<MachineInstr *> InstsToMove,
const SIInstrInfo *TII, AliasAnalysis *AA) { AliasAnalysis *AA) {
assert(MemOp.mayLoadOrStore()); assert(MemOp.mayLoadOrStore());
for (MachineInstr *InstToMove : InstsToMove) { for (MachineInstr *InstToMove : InstsToMove) {
if (!InstToMove->mayLoadOrStore()) if (!InstToMove->mayLoadOrStore())
continue; continue;
if (!memAccessesCanBeReordered(MemOp, *InstToMove, TII, AA)) if (!memAccessesCanBeReordered(MemOp, *InstToMove, AA))
return false; return false;
} }
return true; return true;
Context not available.
} }
if (MBBI->mayLoadOrStore() && if (MBBI->mayLoadOrStore() &&
(!memAccessesCanBeReordered(*CI.I, *MBBI, TII, AA) || (!memAccessesCanBeReordered(*CI.I, *MBBI, AA) ||
!canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, TII, AA))) { !canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, AA))) {
// We fail condition #1, but we may still be able to satisfy condition // We fail condition #1, but we may still be able to satisfy condition
// #2. Add this instruction to the move list and then we will check // #2. Add this instruction to the move list and then we will check
// if condition #2 holds once we have selected the matching instruction. // if condition #2 holds once we have selected the matching instruction.
Context not available.
// move and make sure they are all safe to move down past the merged // move and make sure they are all safe to move down past the merged
// instruction. // instruction.
if (widthsFit(*STM, CI) && offsetsCanBeCombined(CI)) if (widthsFit(*STM, CI) && offsetsCanBeCombined(CI))
if (canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, TII, AA)) if (canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, AA))
return true; return true;
} }
Context not available.
// it was safe to move I and also all the instruction in InstsToMove // it was safe to move I and also all the instruction in InstsToMove
// down past this instruction. // down past this instruction.
// check if we can move I across MBBI and if we can move all I's users // check if we can move I across MBBI and if we can move all I's users
if (!memAccessesCanBeReordered(*CI.I, *MBBI, TII, AA) || if (!memAccessesCanBeReordered(*CI.I, *MBBI, AA) ||
!canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, TII, AA)) !canMoveInstsAcrossMemOp(*MBBI, CI.InstsToMove, AA))
break; break;
} }
return false; return false;
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test/CodeGen/AMDGPU/ds-combine-with-dependence.ll

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; The second load depends on the store. We can combine the two loads, and the combined load is ; The second load depends on the store. We can combine the two loads, and the combined load is
; at the oroginal place of the second load. ; at the original place of the second load.
; GCN-LABEL: {{^}}ds_combine_RAW ; GCN-LABEL: {{^}}ds_combine_RAW
Context not available.