[mips] Add names and tests for the hardware registers

[dsanders]

LGTM with a nit, hwr_ulr added, and the FIXME comments about the .set directives.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1760 ↗

(On Diff #14843)

Could you add 'hwr_ulr' ($29) too? GAS doesn't accept it at the moment, but it's in the spec.

2255 ↗

(On Diff #14843)

Nit: Multiple blank lines

test/MC/Mips/mips-hwr-register-names.s

6–9 ↗

(On Diff #14843)

Could you add a FIXME comment about the .set lines?

Eventually, I'd like the instruction printer for rdhwr to stop printing the .set directives around it (this doesn't need to be done in this patch). It makes some sense for CodeGen to do emit them but not for the assembler.

test/MC/Mips/mips32r2/valid.s

140–143 ↗

(On Diff #14843)

I'd like to remove the checks for the .set directives but the encoding is on the '.set pop' line so we'd have to keep that for the moment. It would look strange to have a .set pop without a .set push so let's leave the .set directives in the test for now.

Could you add a FIXME comment about them?

[vkalintiris]

Closed by commit rL221299 (authored by @vkalintiris).

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

bool parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI,
                        StringRef Directive);
 
   MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
 
   bool eatComma(StringRef ErrorStr);
 
   int matchCPURegisterName(StringRef Symbol);
 
+  int matchHWRegsRegisterName(StringRef Symbol);
+
   int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
 
   int matchFPURegisterName(StringRef Name);
 
   int matchFCCRegisterName(StringRef Name);
 
   int matchACRegisterName(StringRef Name);
 
public:
   /// Create a register that is definitely a FGR.
   /// This is typically only used for named registers such as $f0.
   static std::unique_ptr<MipsOperand>
   createFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
                MipsAsmParser &Parser) {
     return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser);
   }
 
+  /// Create a register that is definitely a HWReg.
+  /// This is typically only used for named registers such as $hwr_cpunum.
+  static std::unique_ptr<MipsOperand>
+  createHWRegsReg(unsigned Index, const MCRegisterInfo *RegInfo,
+                  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
+    return CreateReg(Index, RegKind_HWRegs, RegInfo, S, E, Parser);
+  }
+
   /// Create a register that is definitely an FCC.
   /// This is typically only used for named registers such as $fcc0.
   static std::unique_ptr<MipsOperand>
   createFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
                MipsAsmParser &Parser) {
     return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser);
   }
 
CC = StringSwitch<unsigned>(Name)
              .Case("a7", 11)
              .Case("kt0", 26)
              .Case("kt1", 27)
              .Default(-1);
 
   return CC;
 }
 
+int MipsAsmParser::matchHWRegsRegisterName(StringRef Name) {
+  int CC;
+
+  CC = StringSwitch<unsigned>(Name)
+           .Case("hwr_cpunum", 0)
+           .Case("hwr_synci_step", 1)
+           .Case("hwr_cc", 2)
+           .Case("hwr_ccres", 3)
+           .Case("hwr_ulr", 29)
+           .Default(-1);
+
+  return CC;
+}
+
 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
 
   if (Name[0] == 'f') {
     StringRef NumString = Name.substr(1);
     unsigned IntVal;
     if (NumString.getAsInteger(10, IntVal))
       return -1;     // This is not an integer.
     if (IntVal > 31) // Maximum index for fpu register.
MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
                                                  SMLoc S) {
   int Index = matchCPURegisterName(Identifier);
   if (Index != -1) {
     Operands.push_back(MipsOperand::createGPRReg(
         Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
     return MatchOperand_Success;
   }
 
+  Index = matchHWRegsRegisterName(Identifier);
+  if (Index != -1) {
+    Operands.push_back(MipsOperand::createHWRegsReg(
+        Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
+    return MatchOperand_Success;
+  }
+
   Index = matchFPURegisterName(Identifier);
   if (Index != -1) {
     Operands.push_back(MipsOperand::createFGRReg(
         Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
     return MatchOperand_Success;
   }
 
   Index = matchFCCRegisterName(Identifier);

llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td

let Namespace = "Mips" in {
 
   // COP3 registers.
   foreach I = 0-31 in
   def COP3#I : MipsReg<#I, ""#I>;
 
   // PC register
   def PC : Register<"pc">;
 
-  // Hardware register $29
-  foreach I = 0-31 in
+  // Hardware registers
+  def HWR0 : MipsReg<0, "hwr_cpunum">;
+  def HWR1 : MipsReg<1, "hwr_synci_step">;
+  def HWR2 : MipsReg<2, "hwr_cc">;
+  def HWR3 : MipsReg<3, "hwr_ccres">;
+  def HWR29 : MipsReg<29, "hwr_ulr">;
+
+  foreach I = {4-28,30-31} in
   def HWR#I : MipsReg<#I, ""#I>;
 
   // Accum registers
   foreach I = 0-3 in
   def AC#I : ACCReg<#I, "ac"#I,
                     [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>;
 
   def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>;

llvm/trunk/test/CodeGen/Mips/tls.ll

 ; PIC-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
 ; PIC-DAG:   addiu   $4, $[[R0]], %tlsgd(t1)
 ; PIC-DAG:   jalr    $25
 ; PIC-DAG:   lw      $2, 0($2)
 
 ; STATIC-LABEL:   f1:
 ; STATIC:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
 ; STATIC:   addiu   $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
-; STATIC:   rdhwr   $3, $29
+; STATIC:   rdhwr   $3, $hwr_ulr
 ; STATIC:   addu    $[[R2:[0-9]+]], $3, $[[R1]]
 ; STATIC:   lw      $2, 0($[[R2]])
 }
 
 
 @t2 = external thread_local global i32
 
 define i32 @f2() nounwind {

 ; STATICGP-LABEL: f2:
 ; STATICGP: lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATICGP: addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
 ; STATICGP: lw      ${{[0-9]+}}, %gottprel(t2)($[[GP]])
 
 ; STATIC-LABEL:   f2:
 ; STATIC:   lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATIC:   addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
-; STATIC:   rdhwr   $3, $29
+; STATIC:   rdhwr   $3, $hwr_ulr
 ; STATIC:   lw      $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
 ; STATIC:   addu    $[[R1:[0-9]+]], $3, $[[R0]]
 ; STATIC:   lw      $2, 0($[[R1]])
 }
 
 @f3.i = internal thread_local unnamed_addr global i32 1, align 4
 
 define i32 @f3() nounwind {

llvm/trunk/test/MC/Mips/mips-alu-instructions.s

 # CHECK:  addi   $sp, $sp, -56   # encoding: [0xc8,0xff,0xbd,0x23]
 # CHECK:  subu   $4, $3, $5      # encoding: [0x23,0x20,0x65,0x00]
 # CHECK:  addiu   $sp, $sp, -40  # encoding: [0xd8,0xff,0xbd,0x27]
 # CHECK:  neg     $6, $7         # encoding: [0x22,0x30,0x07,0x00]
 # CHECK:  negu    $6, $7         # encoding: [0x23,0x30,0x07,0x00]
 # CHECK:  move    $7, $8         # encoding: [0x21,0x38,0x00,0x01]
 # CHECK:  .set    push
 # CHECK:  .set    mips32r2
-# CHECK:  rdhwr   $5, $29
+# CHECK:  rdhwr   $5, $hwr_ulr
 # CHECK:  .set    pop            # encoding: [0x3b,0xe8,0x05,0x7c]
     add    $9,$6,$7
     add    $9,$6,17767
     addu   $9,$6,-15001
     addi   $9,$6,17767
     addi   $9,17767
     addiu  $9,$6,-15001
     addiu  $11,40

llvm/trunk/test/MC/Mips/mips-hwr-register-names.s

+# Check the hardware registers
+#
+# FIXME: Use the code generator in order to print the .set directives
+#        instead of the instruction printer.
+#
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | \
+# RUN:      FileCheck %s
+        .set noat
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $hwr_cpunum
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x00,0x3b]
+        rdhwr     $a0,$hwr_cpunum
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $hwr_cpunum
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x00,0x3b]
+        rdhwr     $a0,$0
+
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $5, $hwr_synci_step
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x05,0x08,0x3b]
+        rdhwr     $a1,$hwr_synci_step
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $5, $hwr_synci_step
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x05,0x08,0x3b]
+        rdhwr     $a1,$1
+
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $6, $hwr_cc
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x06,0x10,0x3b]
+        rdhwr     $a2,$hwr_cc
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $6, $hwr_cc
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x06,0x10,0x3b]
+        rdhwr     $a2,$2
+
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $7, $hwr_ccres
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x07,0x18,0x3b]
+        rdhwr     $a3,$hwr_ccres
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $7, $hwr_ccres
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x07,0x18,0x3b]
+        rdhwr     $a3,$3
+
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $4
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x20,0x3b]
+        rdhwr     $a0,$4
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $5
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x28,0x3b]
+        rdhwr     $a0,$5
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $6
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x30,0x3b]
+        rdhwr     $a0,$6
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $7
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x38,0x3b]
+        rdhwr     $a0,$7
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $8
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x40,0x3b]
+        rdhwr     $a0,$8
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $9
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x48,0x3b]
+        rdhwr     $a0,$9
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $10
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x50,0x3b]
+        rdhwr     $a0,$10
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $11
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x58,0x3b]
+        rdhwr     $a0,$11
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $12
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x60,0x3b]
+        rdhwr     $a0,$12
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $13
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x68,0x3b]
+        rdhwr     $a0,$13
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $14
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x70,0x3b]
+        rdhwr     $a0,$14
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $15
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x78,0x3b]
+        rdhwr     $a0,$15
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $16
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x80,0x3b]
+        rdhwr     $a0,$16
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $17
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x88,0x3b]
+        rdhwr     $a0,$17
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $18
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x90,0x3b]
+        rdhwr     $a0,$18
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $19
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0x98,0x3b]
+        rdhwr     $a0,$19
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $20
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xa0,0x3b]
+        rdhwr     $a0,$20
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $21
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xa8,0x3b]
+        rdhwr     $a0,$21
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $22
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xb0,0x3b]
+        rdhwr     $a0,$22
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $23
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xb8,0x3b]
+        rdhwr     $a0,$23
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $24
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xc0,0x3b]
+        rdhwr     $a0,$24
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $25
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xc8,0x3b]
+        rdhwr     $a0,$25
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $26
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xd0,0x3b]
+        rdhwr     $a0,$26
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $27
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xd8,0x3b]
+        rdhwr     $a0,$27
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $28
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xe0,0x3b]
+        rdhwr     $a0,$28
+
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $hwr_ulr
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xe8,0x3b]
+        rdhwr     $a0,$hwr_ulr
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $hwr_ulr
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xe8,0x3b]
+        rdhwr     $a0,$29
+
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $30
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xf0,0x3b]
+        rdhwr     $a0,$30
+        # CHECK:      .set    push
+        # CHECK-NEXT: .set    mips32r2
+        # CHECK-NEXT: rdhwr   $4, $31
+        # CHECK-NEXT: .set    pop             # encoding: [0x7c,0x04,0xf8,0x3b]
+        rdhwr     $a0,$31

llvm/trunk/test/MC/Mips/mips32r2/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
         nmsub.d   $f30,$f8,$f16,$f30
         nmsub.s   $f1,$f24,$f19,$f4
         nop
         nor       $a3,$zero,$a3
         or        $12,$s0,$sp
         or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
         pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
         pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
-        rdhwr     $sp,$11              
+        # FIXME: Use the code generator in order to print the .set directives
+        #        instead of the instruction printer.
+        rdhwr     $sp,$11              # CHECK:      .set  push
+                                       # CHECK-NEXT: .set  mips32r2
+                                       # CHECK-NEXT: rdhwr $sp, $11
+                                       # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
         rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
         rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
         rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
         round.w.d $f6,$f4
         round.w.s $f27,$f28
         sb        $s6,-19857($14)
         sc        $15,18904($s3)       # CHECK: sc $15, 18904($19)     # encoding: [0xe2,0x6f,0x49,0xd8]
         sdbbp                          # CHECK: sdbbp                  # encoding: [0x70,0x00,0x00,0x3f]

llvm/trunk/test/MC/Mips/mips32r6/valid.s

# RUN: FileCheck %s -check-prefix=WARNING < %t0
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
         mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
         muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]
         maddf.s $f2,$f3,$f4      # CHECK: maddf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x98]
         maddf.d $f2,$f3,$f4      # CHECK: maddf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x98]
         msubf.s $f2,$f3,$f4      # CHECK: msubf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x99]
         msubf.d $f2,$f3,$f4      # CHECK: msubf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x99]
         pref    1, 8($5)         # CHECK: pref 1, 8($5)          # encoding: [0x7c,0xa1,0x04,0x35]
+        # FIXME: Use the code generator in order to print the .set directives
+        #        instead of the instruction printer.
+        rdhwr   $sp,$11          # CHECK:      .set  push
+                                 # CHECK-NEXT: .set  mips32r2
+                                 # CHECK-NEXT: rdhwr $sp, $11
+                                 # CHECK-NEXT: .set  pop      # encoding: [0x7c,0x1d,0x58,0x3b]
         sel.d   $f0,$f1,$f2      # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
         sel.s   $f0,$f1,$f2      # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]
         seleqz  $2,$3,$4         # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35]
         selnez  $2,$3,$4         # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37]
         max.s   $f0, $f2, $f4    # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d]
         max.d   $f0, $f2, $f4    # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d]
         min.s   $f0, $f2, $f4    # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c]
         min.d   $f0, $f2, $f4    # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c]

llvm/trunk/test/MC/Mips/mips64-alu-instructions.s

 # CHECK:  mult   $3, $5          # encoding: [0x18,0x00,0x65,0x00]
 # CHECK:  multu  $3, $5          # encoding: [0x19,0x00,0x65,0x00]
 # CHECK:  dsub    $9, $6, $7     # encoding: [0x2e,0x48,0xc7,0x00]
 # CHECK:  dsubu   $4, $3, $5     # encoding: [0x2f,0x20,0x65,0x00]
 # CHECK:  daddiu  $9, $6, -17767 # encoding: [0x99,0xba,0xc9,0x64]
 # CHECK:  move    $7, $8         # encoding: [0x2d,0x38,0x00,0x01]
 # CHECK:  .set    push
 # CHECK:  .set    mips32r2
-# CHECK:  rdhwr   $5, $29
+# CHECK:  rdhwr   $5, $hwr_ulr
 # CHECK:  .set    pop            # encoding: [0x3b,0xe8,0x05,0x7c]
 
     dadd    $9,$6,$7
     dadd    $9,$6,17767
     daddu   $9,$6,-15001
     daddi   $9,$6,17767
     daddi   $9,17767
     daddiu  $9,$6,-15001

llvm/trunk/test/MC/Mips/mips64r2/valid.s

# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
         nmadd.s   $f0,$f5,$f25,$f12
         nmsub.s   $f1,$f24,$f19,$f4
         nop
         nor       $a3,$zero,$a3
         or        $12,$s0,$sp
         or        $2, 4                # CHECK: ori $2, $2, 4           # encoding: [0x34,0x42,0x00,0x04]
         pause                          # CHECK: pause # encoding:  [0x00,0x00,0x01,0x40]
         pref      1, 8($5)             # CHECK: pref 1, 8($5)           # encoding: [0xcc,0xa1,0x00,0x08]
-        rdhwr     $sp,$11
+        # FIXME: Use the code generator in order to print the .set directives
+        #        instead of the instruction printer.
+        rdhwr     $sp,$11              # CHECK:      .set  push
+                                       # CHECK-NEXT: .set  mips32r2
+                                       # CHECK-NEXT: rdhwr $sp, $11
+                                       # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
         rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
         rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
         rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
         round.l.d $f12,$f1
         round.l.s $f25,$f5
         round.w.d $f6,$f4
         round.w.s $f27,$f28
         sb        $s6,-19857($14)

llvm/trunk/test/MC/Mips/mips64r6/valid.s

# RUN: FileCheck %s -check-prefix=WARNING < %t0
         maxa.d  $f0, $f2, $f4    # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f]
         mina.s  $f0, $f2, $f4    # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
         mina.d  $f0, $f2, $f4    # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]
         or      $2, 4            # CHECK: ori $2, $2, 4          # encoding: [0x34,0x42,0x00,0x04]
         seleqz.s $f0, $f2, $f4   # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14]
         seleqz.d $f0, $f2, $f4   # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14]
         selnez.s $f0, $f2, $f4   # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17]
         selnez.d $f0, $f2, $f4   # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17]
+        # FIXME: Use the code generator in order to print the .set directives
+        #        instead of the instruction printer.
+        rdhwr   $sp,$11          # CHECK:      .set  push
+                                 # CHECK-NEXT: .set  mips32r2
+                                 # CHECK-NEXT: rdhwr $sp, $11
+                                 # CHECK-NEXT: .set  pop         # encoding: [0x7c,0x1d,0x58,0x3b]
         rint.s $f2, $f4          # CHECK: rint.s $f2, $f4        # encoding: [0x46,0x00,0x20,0x9a]
         rint.d $f2, $f4          # CHECK: rint.d $f2, $f4        # encoding: [0x46,0x20,0x20,0x9a]
         class.s $f2, $f4         # CHECK: class.s $f2, $f4       # encoding: [0x46,0x00,0x20,0x9b]
         class.d $f2, $f4         # CHECK: class.d $f2, $f4       # encoding: [0x46,0x20,0x20,0x9b]
         jr.hb   $4               # CHECK: jr.hb $4               # encoding: [0x00,0x80,0x04,0x09]
         jalr.hb $4               # CHECK: jalr.hb $4             # encoding: [0x00,0x80,0xfc,0x09]
         jalr.hb $4, $5           # CHECK: jalr.hb $4, $5         # encoding: [0x00,0xa0,0x24,0x09]
         ldc2    $8, -701($at)    # CHECK: ldc2 $8, -701($1)      # encoding: [0x49,0xc8,0x0d,0x43]