[X86] Add some missing blsr patterns

[GBuella]

Summary

The add+and sequence followed by a branch can happen e.g. when looping over the set bits of an integer:

while (x != 0) {
   func(x & ~x);
   x &= x - 1;
}

[GBuella]

The two corresponding test cases are not yet commited,
https://reviews.llvm.org/D57297

[craig.topper]

LGTM

llvm/lib/Target/X86/X86InstrInfo.td

   return hasNoCarryFlagUses(SDValue(N, 1));
 }]>;
 
 def xor_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
                             (X86xor_flag node:$lhs, node:$rhs), [{
   return hasNoCarryFlagUses(SDValue(N, 1));
 }]>;
 
+def and_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
+                            (X86and_flag node:$lhs, node:$rhs), [{
+  return hasNoCarryFlagUses(SDValue(N, 1));
+}]>;
+
 let Predicates = [HasBMI] in {
   // FIXME: patterns for the load versions are not implemented
   def : Pat<(and GR32:$src, (add GR32:$src, -1)),
             (BLSR32rr GR32:$src)>;
   def : Pat<(and GR64:$src, (add GR64:$src, -1)),
             (BLSR64rr GR64:$src)>;
 
   def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
             (BLSMSK32rr GR32:$src)>;
   def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
             (BLSMSK64rr GR64:$src)>;
 
   def : Pat<(and GR32:$src, (ineg GR32:$src)),
             (BLSI32rr GR32:$src)>;
   def : Pat<(and GR64:$src, (ineg GR64:$src)),
             (BLSI64rr GR64:$src)>;
 
   // Versions to match flag producing ops.
-  // X86and_flag nodes are rarely created. Those should use CMP+AND. We do
-  // TESTrr matching in PostProcessISelDAG to allow BLSR/BLSI to be formed.
   def : Pat<(xor_flag_nocf GR32:$src, (add GR32:$src, -1)),
             (BLSMSK32rr GR32:$src)>;
   def : Pat<(xor_flag_nocf GR64:$src, (add GR64:$src, -1)),
             (BLSMSK64rr GR64:$src)>;
+
+  def : Pat<(and_flag_nocf GR32:$src, (add GR32:$src, -1)),
+            (BLSR32rr GR32:$src)>;
+  def : Pat<(and_flag_nocf GR64:$src, (add GR64:$src, -1)),
+            (BLSR64rr GR64:$src)>;
 }
 
 multiclass bmi_bextr<bits<8> opc, string mnemonic, RegisterClass RC,
                      X86MemOperand x86memop, SDNode OpNode,
                      PatFrag ld_frag, X86FoldableSchedWrite Sched> {
   def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
              !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
              [(set RC:$dst, (OpNode RC:$src1, RC:$src2)), (implicit EFLAGS)]>,

llvm/test/CodeGen/X86/bmi.ll

 }
 
 define i32 @blsr32_branch(i32 %x) {
 ; X86-LABEL: blsr32_branch:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    .cfi_offset %esi, -8
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    leal -1(%eax), %esi
-; X86-NEXT:    andl %eax, %esi
+; X86-NEXT:    blsrl {{[0-9]+}}(%esp), %esi
 ; X86-NEXT:    jne .LBB46_2
 ; X86-NEXT:  # %bb.1:
 ; X86-NEXT:    calll bar
 ; X86-NEXT:  .LBB46_2:
 ; X86-NEXT:    movl %esi, %eax
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: blsr32_branch:
 ; X64:       # %bb.0:
 ; X64-NEXT:    pushq %rbx
 ; X64-NEXT:    .cfi_def_cfa_offset 16
 ; X64-NEXT:    .cfi_offset %rbx, -16
-; X64-NEXT:    # kill: def $edi killed $edi def $rdi
-; X64-NEXT:    leal -1(%rdi), %ebx
-; X64-NEXT:    andl %edi, %ebx
+; X64-NEXT:    blsrl %edi, %ebx
 ; X64-NEXT:    jne .LBB46_2
 ; X64-NEXT:  # %bb.1:
 ; X64-NEXT:    callq bar
 ; X64-NEXT:  .LBB46_2:
 ; X64-NEXT:    movl %ebx, %eax
 ; X64-NEXT:    popq %rbx
 ; X64-NEXT:    .cfi_def_cfa_offset 8
 ; X64-NEXT:    retq

 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: blsr64_branch:
 ; X64:       # %bb.0:
 ; X64-NEXT:    pushq %rbx
 ; X64-NEXT:    .cfi_def_cfa_offset 16
 ; X64-NEXT:    .cfi_offset %rbx, -16
-; X64-NEXT:    leaq -1(%rdi), %rbx
-; X64-NEXT:    andq %rdi, %rbx
+; X64-NEXT:    blsrq %rdi, %rbx
 ; X64-NEXT:    jne .LBB47_2
 ; X64-NEXT:  # %bb.1:
 ; X64-NEXT:    callq bar
 ; X64-NEXT:  .LBB47_2:
 ; X64-NEXT:    movq %rbx, %rax
 ; X64-NEXT:    popq %rbx
 ; X64-NEXT:    .cfi_def_cfa_offset 8
 ; X64-NEXT:    retq