[X86] Fold X86ISD::SBB(ISD::SUB(X,Y),0) -> X86ISD::SBB(X,Y) (PR25858)

[RKSimon]

Summary

We often generate X86ISD::SBB(X, 0) for carry flag arithmetic.

I had tried to create test cases for the ADC equivalent (which often uses the same pattern) but haven't managed to find anything yet.

[craig.topper]

lib/Target/X86/X86ISelLowering.cpp

40510

This is only valid if the flag result of the SBB is dead. If the sub(X,Y) had a borrow, that information was silently dropped. The SBB output flag should only be calculating the borrow from the result of the subtract minus the C flag. By folding them it would calculate the C flag based on the combined subtraction.

This is the same reason DAGCombiner::visitADDCARRYLike has a check that the ADDCARRY flag result isn't used.

[RKSimon]

lib/Target/X86/X86ISelLowering.cpp

40510

LOL - I realised that walking home. I'll take another look.

[RKSimon]

Limit the combine to cases where we don't use the output overflow flag

[RKSimon]

@craig.topper Does this look ok now?

[craig.topper]

LGTM

lib/Target/X86/X86ISelLowering.cpp

static SDValue combineSBB(SDNode *N, SelectionDAG &DAG) {
   if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
     MVT VT = N->getSimpleValueType(0);
     SDVTList VTs = DAG.getVTList(VT, MVT::i32);
     return DAG.getNode(X86ISD::SBB, SDLoc(N), VTs,
                        N->getOperand(0), N->getOperand(1),
                        Flags);
   }
 
+  // Fold SBB(SUB(X,Y),0) -> SBB(X,Y)
+  SDValue Op0 = N->getOperand(0);
+  SDValue Op1 = N->getOperand(1);
+  if (Op0.getOpcode() == ISD::SUB && isNullConstant(Op1))
+    return DAG.getNode(X86ISD::SBB, SDLoc(N), N->getVTList(), Op0.getOperand(0),
+                       Op0.getOperand(1), N->getOperand(2));
+
   return SDValue();
 }
 
 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
 static SDValue combineADC(SDNode *N, SelectionDAG &DAG,
                           TargetLowering::DAGCombinerInfo &DCI) {
   // If the LHS and RHS of the ADC node are zero, then it can't overflow and
   // the result is either zero or one (depending on the input carry bit).

test/CodeGen/X86/combine-sbb.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64
 
 %WideUInt32 = type { i32, i32 }
 
 define void @PR25858_i32(%WideUInt32* sret, %WideUInt32*, %WideUInt32*) nounwind {
 ; X86-LABEL: PR25858_i32:
 ; X86:       # %bb.0: # %top
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT:    movl (%edx), %esi
-; X86-NEXT:    movl 4(%edx), %edx
-; X86-NEXT:    subl 4(%ecx), %edx
-; X86-NEXT:    subl (%ecx), %esi
-; X86-NEXT:    sbbl $0, %edx
+; X86-NEXT:    movl (%ecx), %esi
+; X86-NEXT:    movl 4(%ecx), %ecx
+; X86-NEXT:    subl (%edx), %esi
+; X86-NEXT:    sbbl 4(%edx), %ecx
+; X86-NEXT:    movl %ecx, 4(%eax)
 ; X86-NEXT:    movl %esi, (%eax)
-; X86-NEXT:    movl %edx, 4(%eax)
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    retl $4
 ;
 ; X64-LABEL: PR25858_i32:
 ; X64:       # %bb.0: # %top
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    movl (%rsi), %ecx
 ; X64-NEXT:    movl 4(%rsi), %esi
-; X64-NEXT:    subl 4(%rdx), %esi
 ; X64-NEXT:    subl (%rdx), %ecx
-; X64-NEXT:    sbbl $0, %esi
-; X64-NEXT:    movl %ecx, (%rdi)
+; X64-NEXT:    sbbl 4(%rdx), %esi
 ; X64-NEXT:    movl %esi, 4(%rdi)
+; X64-NEXT:    movl %ecx, (%rdi)
 ; X64-NEXT:    retq
 top:
   %3 = bitcast %WideUInt32* %1 to i32*
   %4 = load i32, i32* %3, align 4
   %5 = bitcast %WideUInt32* %2 to i32*
   %6 = load i32, i32* %5, align 4
   %7 = sub i32 %4, %6
   %8 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %4, i32 %6)

 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    retl $4
 ;
 ; X64-LABEL: PR25858_i64:
 ; X64:       # %bb.0: # %top
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    movq (%rsi), %rcx
 ; X64-NEXT:    movq 8(%rsi), %rsi
-; X64-NEXT:    subq 8(%rdx), %rsi
 ; X64-NEXT:    subq (%rdx), %rcx
-; X64-NEXT:    sbbq $0, %rsi
-; X64-NEXT:    movq %rcx, (%rdi)
+; X64-NEXT:    sbbq 8(%rdx), %rsi
 ; X64-NEXT:    movq %rsi, 8(%rdi)
+; X64-NEXT:    movq %rcx, (%rdi)
 ; X64-NEXT:    retq
 top:
   %3 = bitcast %WideUInt64* %1 to i64*
   %4 = load i64, i64* %3, align 8
   %5 = bitcast %WideUInt64* %2 to i64*
   %6 = load i64, i64* %5, align 8
   %7 = sub i64 %4, %6
   %8 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %4, i64 %6)