[X86] Add a one use check to the setcc inversion code in combineVSelectWithAllOnesOrZeros

[craig.topper]

Summary

If we're going to generate a new inverted setcc, we should make sure we will be able to remove the old setcc.

This found in a larger test case from a coworker I haven't had a chance to reduce yet.

[RKSimon]

LGTM but a test case would be useful.

lib/Target/X86/X86ISelLowering.cpp

33851 ↗

(On Diff #181943)

Update comment?

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
   // vector floating-point selects.
   if (CondVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
     return SDValue();
 
   bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
   bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
 
   // Try to invert the condition if true value is not all 1s and false value is
-  // not all 0s.
-  if (!TValIsAllOnes && !FValIsAllZeros &&
+  // not all 0s. Only do this if the condition has one use.
+  if (!TValIsAllOnes && !FValIsAllZeros && Cond.hasOneUse() &&
       // Check if the selector will be produced by CMPP*/PCMP*.
       Cond.getOpcode() == ISD::SETCC &&
       // Check if SETCC has already been promoted.
       TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
           CondVT) {
     bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
 
     if (TValIsAllZeros || FValIsAllOnes) {

llvm/trunk/test/CodeGen/X86/vselect.ll

 
 ; Test to make sure we don't try to insert a new setcc to swap the operands
 ; of select with all zeros LHS if the setcc has additional users.
 define void @vselect_allzeros_LHS_multiple_use_setcc(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32>* %p1, <4 x i32>* %p2) {
 ; SSE-LABEL: vselect_allzeros_LHS_multiple_use_setcc:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    movdqa {{.*#+}} xmm3 = [1,2,4,8]
 ; SSE-NEXT:    pand %xmm3, %xmm0
-; SSE-NEXT:    pcmpeqd %xmm0, %xmm3
-; SSE-NEXT:    pxor %xmm4, %xmm4
-; SSE-NEXT:    pcmpeqd %xmm0, %xmm4
-; SSE-NEXT:    pand %xmm1, %xmm4
-; SSE-NEXT:    pand %xmm2, %xmm3
-; SSE-NEXT:    movdqa %xmm4, (%rdi)
-; SSE-NEXT:    movdqa %xmm3, (%rsi)
+; SSE-NEXT:    pcmpeqd %xmm3, %xmm0
+; SSE-NEXT:    movdqa %xmm0, %xmm3
+; SSE-NEXT:    pandn %xmm1, %xmm3
+; SSE-NEXT:    pand %xmm2, %xmm0
+; SSE-NEXT:    movdqa %xmm3, (%rdi)
+; SSE-NEXT:    movdqa %xmm0, (%rsi)
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: vselect_allzeros_LHS_multiple_use_setcc:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vmovdqa {{.*#+}} xmm3 = [1,2,4,8]
 ; AVX-NEXT:    vpand %xmm3, %xmm0, %xmm0
-; AVX-NEXT:    vpcmpeqd %xmm3, %xmm0, %xmm3
-; AVX-NEXT:    vpxor %xmm4, %xmm4, %xmm4
-; AVX-NEXT:    vpcmpeqd %xmm4, %xmm0, %xmm0
-; AVX-NEXT:    vpand %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpand %xmm2, %xmm3, %xmm1
-; AVX-NEXT:    vmovdqa %xmm0, (%rdi)
-; AVX-NEXT:    vmovdqa %xmm1, (%rsi)
+; AVX-NEXT:    vpcmpeqd %xmm3, %xmm0, %xmm0
+; AVX-NEXT:    vpandn %xmm1, %xmm0, %xmm1
+; AVX-NEXT:    vpand %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vmovdqa %xmm1, (%rdi)
+; AVX-NEXT:    vmovdqa %xmm0, (%rsi)
 ; AVX-NEXT:    retq
   %and = and <4 x i32> %x, <i32 1, i32 2, i32 4, i32 8>
   %cond = icmp ne <4 x i32> %and, zeroinitializer
   %sel1 = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %y
   %sel2 = select <4 x i1> %cond, <4 x i32> %z, <4 x i32> zeroinitializer
   store <4 x i32> %sel1, <4 x i32>* %p1
   store <4 x i32> %sel2, <4 x i32>* %p2
   ret void
 }