[X86] Avoid clobbering ESP/RSP in the epilogue.

[goffrie]

Summary

In r345197 ESP and RSP were added to GR32_TC/GR64_TC, allowing them to
be used for tail calls, but this also caused findDeadCallerSavedReg to
think they were acceptable targets for clobbering. Filter them out.

Fixes PR40289.

[rnk]

Thanks for the report and patch! Looks good. Do you need someone to commit this?

test/CodeGen/X86/pr40289-64bit.ll

6

popq %rsp, hilarious. XD

[goffrie]

I don't have commit access, so if you could commit it for me, I'd appreciate it!

lib/Target/X86/X86FrameLowering.cpp

for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
       unsigned Reg = MO.getReg();
       if (!Reg)
         continue;
       for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
         Uses.insert(*AI);
     }
 
     for (auto CS : AvailableRegs)
-      if (!Uses.count(CS) && CS != X86::RIP)
+      if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP &&
+          CS != X86::ESP)
         return CS;
   }
   }
 
   return 0;
 }
 
 static bool isEAXLiveIn(MachineBasicBlock &MBB) {

test/CodeGen/X86/pr40289-64bit.ll

+; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc | FileCheck %s
+
+define cc 92 < 9 x i64 > @clobber() {
+  %1 = alloca i64
+  %2 = load volatile i64, i64* %1
+  ; CHECK-NOT: popq %rsp
+  ; CHECK: addq $8, %rsp
+  ret < 9 x i64 > undef
+}

test/CodeGen/X86/pr40289.ll

+; RUN: llc < %s -mtriple=i686-pc-windows-msvc | FileCheck %s
+
+define < 3 x i32 > @clobber() {
+  %1 = alloca i32
+  %2 = load volatile i32, i32* %1
+  ; CHECK-NOT: popl %esp
+  ; CHECK: addl $4, %esp
+  ret < 3 x i32 > undef
+}