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Differential D56421

[X86] Call SimplifyDemandedBits on conditions of X86ISD::SHRUNKBLEND
ClosedPublic

Authored by craig.topper on Jan 7 2019, 5:00 PM.

Details

Reviewers
RKSimon
spatel
Commits
rG844f989608e0: [X86] Call SimplifyDemandedBits on conditions of X86ISD::SHRUNKBLEND
rL350875: [X86] Call SimplifyDemandedBits on conditions of X86ISD::SHRUNKBLEND
Summary

There can be additional simplifications after VSELECT is converted to SHRUNKBLEND. So we should call SimplifyDemandedBits

This should help some of the regressions from D56387

Diff Detail

Event Timeline

craig.topper created this revision.Jan 7 2019, 5:00 PM
craig.topper mentioned this in D56387: [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE.
RKSimon added inline comments.Jan 8 2019, 2:48 AM
lib/Target/X86/X86ISelLowering.cpp
34326

Would it be any better to add X86ISD::SHRUNKBLEND handling to X86TargetLowering::SimplifyDemandedBitsForTargetNode directly?

RKSimon added a comment.Jan 8 2019, 8:38 AM

Also, should we remove the similar SimplifyDemandedBits call in combineVSelectToShrunkBlend?

craig.topper added a comment.Jan 8 2019, 10:11 AM
In D56421#1349790, @RKSimon wrote:

Also, should we remove the similar SimplifyDemandedBits call in combineVSelectToShrunkBlend?

The one that decides when to turn VSELECT into SHRUNKBLEND? I don't think we can remove that. We might be able to merge this with it and turn SHRUNKBLEND into SHRUNKBLEND again if another simplification is made. That would probably help with cases where the condition is used multiple times.

craig.topper updated this revision to Diff 180930.Jan 9 2019, 2:11 PM

Reuse combineVSelectToShrunkBlend. This reduces the code and should allow better optimization when the select condition is used by multiple selects.

Diffusion mentioned this in rL350781: [X86] After turning VSELECT into SHRUNKBLEND, make we push the VSELECT into the….Jan 9 2019, 4:18 PM
RKSimon accepted this revision.Jan 10 2019, 1:20 AM

LGTM - thanks

This revision is now accepted and ready to land.Jan 10 2019, 1:20 AM
Closed by commit rL350875: [X86] Call SimplifyDemandedBits on conditions of X86ISD::SHRUNKBLEND (authored by ctopper). · Explain WhyJan 10 2019, 11:09 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
X86/
12 lines
test/
CodeGen/
X86/
2 lines
43 lines
63 lines
33 lines
63 lines

Diff 180930

lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 33,852 Lines • ▼ Show 20 Linesstatic SDValue combineSelectOfTwoConstants(SDNode *N, SelectionDAG &DAG) {
} }
return SDValue(); return SDValue();
} }
/// If this is a *dynamic* select (non-constant condition) and we can match /// If this is a *dynamic* select (non-constant condition) and we can match
/// this node with one of the variable blend instructions, restructure the /// this node with one of the variable blend instructions, restructure the
/// condition so that blends can use the high (sign) bit of each element. /// condition so that blends can use the high (sign) bit of each element.
/// This function will also call SimplfiyDemandedBits on already created
/// SHRUNKBLENDS to perform additional simplifications.
static SDValue combineVSelectToShrunkBlend(SDNode *N, SelectionDAG &DAG, static SDValue combineVSelectToShrunkBlend(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) { const X86Subtarget &Subtarget) {
SDValue Cond = N->getOperand(0); SDValue Cond = N->getOperand(0);
if (N->getOpcode() != ISD::VSELECT || if ((N->getOpcode() != ISD::VSELECT &&
N->getOpcode() != X86ISD::SHRUNKBLEND) ||
ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
return SDValue(); return SDValue();
// Don't optimize before the condition has been transformed to a legal type // Don't optimize before the condition has been transformed to a legal type
// and don't ever optimize vector selects that map to AVX512 mask-registers. // and don't ever optimize vector selects that map to AVX512 mask-registers.
unsigned BitWidth = Cond.getScalarValueSizeInBits(); unsigned BitWidth = Cond.getScalarValueSizeInBits();
if (BitWidth < 8 || BitWidth > 64) if (BitWidth < 8 || BitWidth > 64)
return SDValue(); return SDValue();
Show All 25 Lines if (VT == MVT::v32i8 && !Subtarget.hasAVX2())
return SDValue(); return SDValue();
// There are no 512-bit blend instructions that use sign bits. // There are no 512-bit blend instructions that use sign bits.
if (VT.is512BitVector()) if (VT.is512BitVector())
return SDValue(); return SDValue();
// TODO: Add other opcodes eventually lowered into BLEND. // TODO: Add other opcodes eventually lowered into BLEND.
for (SDNode::use_iterator UI = Cond->use_begin(), UE = Cond->use_end(); for (SDNode::use_iterator UI = Cond->use_begin(), UE = Cond->use_end();
UI != UE; ++UI) UI != UE; ++UI)
if (UI->getOpcode() != ISD::VSELECT || UI.getOperandNo() != 0) if ((UI->getOpcode() != ISD::VSELECT &&
UI->getOpcode() != X86ISD::SHRUNKBLEND) ||
UI.getOperandNo() != 0)
return SDValue(); return SDValue();
APInt DemandedMask(APInt::getSignMask(BitWidth)); APInt DemandedMask(APInt::getSignMask(BitWidth));
KnownBits Known; KnownBits Known;
TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
!DCI.isBeforeLegalizeOps()); !DCI.isBeforeLegalizeOps());
if (!TLI.SimplifyDemandedBits(Cond, DemandedMask, Known, TLO, 0, true)) if (!TLI.SimplifyDemandedBits(Cond, DemandedMask, Known, TLO, 0, true))
return SDValue(); return SDValue();
// If we changed the computation somewhere in the DAG, this change will // If we changed the computation somewhere in the DAG, this change will
// affect all users of Cond. Update all the nodes so that we do not use // affect all users of Cond. Update all the nodes so that we do not use
// the generic VSELECT anymore. Otherwise, we may perform wrong // the generic VSELECT anymore. Otherwise, we may perform wrong
// optimizations as we messed with the actual expectation for the vector // optimizations as we messed with the actual expectation for the vector
// boolean values. // boolean values.
for (SDNode *U : Cond->uses()) { for (SDNode *U : Cond->uses()) {
if (U->getOpcode() == X86ISD::SHRUNKBLEND)
continue;
SDValue SB = DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(U), U->getValueType(0), SDValue SB = DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(U), U->getValueType(0),
Cond, U->getOperand(1), U->getOperand(2)); Cond, U->getOperand(1), U->getOperand(2));
DAG.ReplaceAllUsesOfValueWith(SDValue(U, 0), SB); DAG.ReplaceAllUsesOfValueWith(SDValue(U, 0), SB);
} }
DCI.CommitTargetLoweringOpt(TLO); DCI.CommitTargetLoweringOpt(TLO);
return SDValue(N, 0); return SDValue(N, 0);
} }
▲ Show 20 Lines • Show All 379 Lines • ▼ Show 20 Linesstatic SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// Custom action for SELECT MMX // Custom action for SELECT MMX
if (VT == MVT::x86mmx) { if (VT == MVT::x86mmx) {
LHS = DAG.getBitcast(MVT::i64, LHS); LHS = DAG.getBitcast(MVT::i64, LHS);
RHS = DAG.getBitcast(MVT::i64, RHS); RHS = DAG.getBitcast(MVT::i64, RHS);
SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::i64, Cond, LHS, RHS); SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::i64, Cond, LHS, RHS);
return DAG.getBitcast(VT, newSelect); return DAG.getBitcast(VT, newSelect);
} }
RKSimonUnsubmitted
Not Done
ReplyInline Actions

Would it be any better to add X86ISD::SHRUNKBLEND handling to X86TargetLowering::SimplifyDemandedBitsForTargetNode directly?

RKSimon: Would it be any better to add X86ISD::SHRUNKBLEND handling to X86TargetLowering…
return SDValue(); return SDValue();
} }
/// Combine: /// Combine:
/// (brcond/cmov/setcc .., (cmp (atomic_load_add x, 1), 0), COND_S) /// (brcond/cmov/setcc .., (cmp (atomic_load_add x, 1), 0), COND_S)
/// to: /// to:
/// (brcond/cmov/setcc .., (LADD x, 1), COND_LE) /// (brcond/cmov/setcc .., (LADD x, 1), COND_LE)
/// i.e., reusing the EFLAGS produced by the LOCKed instruction. /// i.e., reusing the EFLAGS produced by the LOCKed instruction.
▲ Show 20 Lines • Show All 8,266 Lines • Show Last 20 Lines

test/CodeGen/X86/avx2-logic.ll

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Linesentry:
%x = xor <4 x i64> %a2, %b %x = xor <4 x i64> %a2, %b
ret <4 x i64> %x ret <4 x i64> %x
} }
define <32 x i8> @vpblendvb(<32 x i1> %cond, <32 x i8> %x, <32 x i8> %y) { define <32 x i8> @vpblendvb(<32 x i1> %cond, <32 x i8> %x, <32 x i8> %y) {
; X32-LABEL: vpblendvb: ; X32-LABEL: vpblendvb:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpsllw $7, %ymm0, %ymm0 ; X32-NEXT: vpsllw $7, %ymm0, %ymm0
; X32-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0
; X32-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0 ; X32-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vpblendvb: ; X64-LABEL: vpblendvb:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpsllw $7, %ymm0, %ymm0 ; X64-NEXT: vpsllw $7, %ymm0, %ymm0
; X64-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0 ; X64-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%min = select <32 x i1> %cond, <32 x i8> %x, <32 x i8> %y %min = select <32 x i1> %cond, <32 x i8> %x, <32 x i8> %y
ret <32 x i8> %min ret <32 x i8> %min
} }
define <8 x i32> @allOnes() nounwind { define <8 x i32> @allOnes() nounwind {
; X32-LABEL: allOnes: ; X32-LABEL: allOnes:
Show All 23 Lines

test/CodeGen/X86/vector-reduce-smax.ll

Show First 20 Lines • Show All 703 Lines • ▼ Show 20 Lines
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psllq $32, %xmm1 ; SSE41-NEXT: psllq $32, %xmm1
; SSE41-NEXT: psrad $31, %xmm1 ; SSE41-NEXT: psrad $31, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,2,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,2,3,3]
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,2,2,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,2,2,3]
; SSE41-NEXT: psrad $31, %xmm3 ; SSE41-NEXT: psrad $31, %xmm3
; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm3, %xmm2 ; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pxor %xmm0, %xmm2 ; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: pxor %xmm1, %xmm0 ; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm4
; SSE41-NEXT: pcmpgtd %xmm2, %xmm4 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm4, %xmm0
; SSE41-NEXT: pand %xmm5, %xmm0 ; SSE41-NEXT: por %xmm2, %xmm0
; SSE41-NEXT: por %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3
; SSE41-NEXT: movd %xmm3, %eax ; SSE41-NEXT: movd %xmm3, %eax
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: test_v2i32: ; AVX1-LABEL: test_v2i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsllq $32, %xmm0, %xmm1 ; AVX1-NEXT: vpsllq $32, %xmm0, %xmm1
; AVX1-NEXT: vpsrad $31, %xmm1, %xmm1 ; AVX1-NEXT: vpsrad $31, %xmm1, %xmm1
▲ Show 20 Lines • Show All 435 Lines • ▼ Show 20 Lines
; SSE41-NEXT: psrad $16, %xmm1 ; SSE41-NEXT: psrad $16, %xmm1
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm3, %xmm2 ; SSE41-NEXT: movdqa %xmm3, %xmm2
; SSE41-NEXT: pxor %xmm0, %xmm2 ; SSE41-NEXT: pxor %xmm0, %xmm2
; SSE41-NEXT: pxor %xmm1, %xmm0 ; SSE41-NEXT: pxor %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm2, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm4
; SSE41-NEXT: pcmpgtd %xmm0, %xmm4 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm4, %xmm0
; SSE41-NEXT: pand %xmm5, %xmm0 ; SSE41-NEXT: por %xmm2, %xmm0
; SSE41-NEXT: por %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1 ; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1
; SSE41-NEXT: movd %xmm1, %eax ; SSE41-NEXT: movd %xmm1, %eax
; SSE41-NEXT: # kill: def $ax killed $ax killed $eax ; SSE41-NEXT: # kill: def $ax killed $ax killed $eax
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: test_v2i16: ; AVX1-LABEL: test_v2i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsllq $48, %xmm0, %xmm1 ; AVX1-NEXT: vpsllq $48, %xmm0, %xmm1
▲ Show 20 Lines • Show All 465 Lines • ▼ Show 20 Lines
; SSE41-NEXT: psrad $24, %xmm1 ; SSE41-NEXT: psrad $24, %xmm1
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm3, %xmm2 ; SSE41-NEXT: movdqa %xmm3, %xmm2
; SSE41-NEXT: pxor %xmm0, %xmm2 ; SSE41-NEXT: pxor %xmm0, %xmm2
; SSE41-NEXT: pxor %xmm1, %xmm0 ; SSE41-NEXT: pxor %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm2, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm4
; SSE41-NEXT: pcmpgtd %xmm0, %xmm4 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm4, %xmm0
; SSE41-NEXT: pand %xmm5, %xmm0 ; SSE41-NEXT: por %xmm2, %xmm0
; SSE41-NEXT: por %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1 ; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1
; SSE41-NEXT: pextrb $0, %xmm1, %eax ; SSE41-NEXT: pextrb $0, %xmm1, %eax
; SSE41-NEXT: # kill: def $al killed $al killed $eax ; SSE41-NEXT: # kill: def $al killed $al killed $eax
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: test_v2i8: ; AVX1-LABEL: test_v2i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsllq $56, %xmm0, %xmm1 ; AVX1-NEXT: vpsllq $56, %xmm0, %xmm1
▲ Show 20 Lines • Show All 677 Lines • Show Last 20 Lines

test/CodeGen/X86/vector-reduce-smin.ll

Show First 20 Lines • Show All 702 Lines • ▼ Show 20 Lines
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psllq $32, %xmm1 ; SSE41-NEXT: psllq $32, %xmm1
; SSE41-NEXT: psrad $31, %xmm1 ; SSE41-NEXT: psrad $31, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,2,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,2,3,3]
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,2,2,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,2,2,3]
; SSE41-NEXT: psrad $31, %xmm3 ; SSE41-NEXT: psrad $31, %xmm3
; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm1, %xmm2 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pxor %xmm0, %xmm2 ; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: pxor %xmm3, %xmm0 ; SSE41-NEXT: pxor %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm4
; SSE41-NEXT: pcmpgtd %xmm2, %xmm4 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm4, %xmm0
; SSE41-NEXT: pand %xmm5, %xmm0 ; SSE41-NEXT: por %xmm2, %xmm0
; SSE41-NEXT: por %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3
; SSE41-NEXT: movd %xmm3, %eax ; SSE41-NEXT: movd %xmm3, %eax
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: test_v2i32: ; AVX1-LABEL: test_v2i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsllq $32, %xmm0, %xmm1 ; AVX1-NEXT: vpsllq $32, %xmm0, %xmm1
; AVX1-NEXT: vpsrad $31, %xmm1, %xmm1 ; AVX1-NEXT: vpsrad $31, %xmm1, %xmm1
▲ Show 20 Lines • Show All 430 Lines • ▼ Show 20 Lines
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
; SSE41-NEXT: psllq $48, %xmm1 ; SSE41-NEXT: psllq $48, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: psrad $31, %xmm0 ; SSE41-NEXT: psrad $31, %xmm0
; SSE41-NEXT: psrad $16, %xmm1 ; SSE41-NEXT: psrad $16, %xmm1
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm3, %xmm2 ; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pxor %xmm0, %xmm2 ; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: pxor %xmm1, %xmm0 ; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm4
; SSE41-NEXT: pcmpgtd %xmm2, %xmm4 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm4, %xmm0
; SSE41-NEXT: pand %xmm5, %xmm0 ; SSE41-NEXT: por %xmm2, %xmm0
; SSE41-NEXT: por %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1 ; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1
; SSE41-NEXT: movd %xmm1, %eax ; SSE41-NEXT: movd %xmm1, %eax
; SSE41-NEXT: # kill: def $ax killed $ax killed $eax ; SSE41-NEXT: # kill: def $ax killed $ax killed $eax
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: test_v2i16: ; AVX1-LABEL: test_v2i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsllq $48, %xmm0, %xmm1 ; AVX1-NEXT: vpsllq $48, %xmm0, %xmm1
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; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
; SSE41-NEXT: psllq $56, %xmm1 ; SSE41-NEXT: psllq $56, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: psrad $31, %xmm0 ; SSE41-NEXT: psrad $31, %xmm0
; SSE41-NEXT: psrad $24, %xmm1 ; SSE41-NEXT: psrad $24, %xmm1
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm3, %xmm2 ; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pxor %xmm0, %xmm2 ; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: pxor %xmm1, %xmm0 ; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm4
; SSE41-NEXT: pcmpgtd %xmm2, %xmm4 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm4, %xmm0
; SSE41-NEXT: pand %xmm5, %xmm0 ; SSE41-NEXT: por %xmm2, %xmm0
; SSE41-NEXT: por %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1 ; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1
; SSE41-NEXT: pextrb $0, %xmm1, %eax ; SSE41-NEXT: pextrb $0, %xmm1, %eax
; SSE41-NEXT: # kill: def $al killed $al killed $eax ; SSE41-NEXT: # kill: def $al killed $al killed $eax
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: test_v2i8: ; AVX1-LABEL: test_v2i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsllq $56, %xmm0, %xmm1 ; AVX1-NEXT: vpsllq $56, %xmm0, %xmm1
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test/CodeGen/X86/vector-reduce-umax.ll

Show First 20 Lines • Show All 754 Lines • ▼ Show 20 Lines
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE41-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm1, %xmm3 ; SSE41-NEXT: movdqa %xmm1, %xmm3
; SSE41-NEXT: pxor %xmm0, %xmm3 ; SSE41-NEXT: pxor %xmm0, %xmm3
; SSE41-NEXT: pxor %xmm2, %xmm0 ; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: movdqa %xmm3, %xmm4 ; SSE41-NEXT: movdqa %xmm3, %xmm4
; SSE41-NEXT: pcmpgtd %xmm0, %xmm4 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE41-NEXT: pcmpgtd %xmm0, %xmm3
; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,2,2]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm4, %xmm0
; SSE41-NEXT: pand %xmm5, %xmm0 ; SSE41-NEXT: por %xmm3, %xmm0
; SSE41-NEXT: por %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE41-NEXT: movd %xmm2, %eax ; SSE41-NEXT: movd %xmm2, %eax
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: test_v2i32: ; AVX1-LABEL: test_v2i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
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; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3],xmm0[4],xmm1[5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3],xmm0[4],xmm1[5,6,7]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE41-NEXT: pmovzxwq {{.*#+}} xmm2 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero ; SSE41-NEXT: pmovzxwq {{.*#+}} xmm2 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm1, %xmm3 ; SSE41-NEXT: movdqa %xmm1, %xmm3
; SSE41-NEXT: por %xmm0, %xmm3 ; SSE41-NEXT: por %xmm0, %xmm3
; SSE41-NEXT: por %xmm2, %xmm0 ; SSE41-NEXT: por %xmm2, %xmm0
; SSE41-NEXT: movdqa %xmm3, %xmm4 ; SSE41-NEXT: movdqa %xmm3, %xmm4
; SSE41-NEXT: pcmpgtd %xmm0, %xmm4 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE41-NEXT: pcmpgtd %xmm0, %xmm3
; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,2,2]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm4, %xmm0
; SSE41-NEXT: pand %xmm5, %xmm0 ; SSE41-NEXT: por %xmm3, %xmm0
; SSE41-NEXT: por %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE41-NEXT: movd %xmm2, %eax ; SSE41-NEXT: movd %xmm2, %eax
; SSE41-NEXT: # kill: def $ax killed $ax killed $eax ; SSE41-NEXT: # kill: def $ax killed $ax killed $eax
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v2i16: ; AVX-LABEL: test_v2i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE41-NEXT: pand {{.*}}(%rip), %xmm1 ; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
; SSE41-NEXT: pmovzxbq {{.*#+}} xmm2 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero ; SSE41-NEXT: pmovzxbq {{.*#+}} xmm2 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm1, %xmm4 ; SSE41-NEXT: movdqa %xmm1, %xmm4
; SSE41-NEXT: por %xmm3, %xmm4 ; SSE41-NEXT: por %xmm3, %xmm4
; SSE41-NEXT: por %xmm2, %xmm3 ; SSE41-NEXT: por %xmm2, %xmm3
; SSE41-NEXT: movdqa %xmm4, %xmm0 ; SSE41-NEXT: movdqa %xmm4, %xmm0
; SSE41-NEXT: pcmpgtd %xmm3, %xmm0 ; SSE41-NEXT: pcmpeqd %xmm3, %xmm0
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm0[0,0,2,2] ; SSE41-NEXT: pcmpgtd %xmm3, %xmm4
; SSE41-NEXT: pcmpeqd %xmm4, %xmm3 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,0,2,2]
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE41-NEXT: pand %xmm3, %xmm0
; SSE41-NEXT: pand %xmm5, %xmm3 ; SSE41-NEXT: por %xmm4, %xmm0
; SSE41-NEXT: por %xmm3, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE41-NEXT: pextrb $0, %xmm2, %eax ; SSE41-NEXT: pextrb $0, %xmm2, %eax
; SSE41-NEXT: # kill: def $al killed $al killed $eax ; SSE41-NEXT: # kill: def $al killed $al killed $eax
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v2i8: ; AVX-LABEL: test_v2i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1 ; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
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test/CodeGen/X86/vector-reduce-umin.ll

Show First 20 Lines • Show All 748 Lines • ▼ Show 20 Lines
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v2i32: ; SSE41-LABEL: test_v2i32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pxor %xmm1, %xmm1 ; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE41-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm1, %xmm3 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pxor %xmm0, %xmm3 ; SSE41-NEXT: pxor %xmm3, %xmm0
; SSE41-NEXT: pxor %xmm2, %xmm0 ; SSE41-NEXT: pxor %xmm2, %xmm3
; SSE41-NEXT: movdqa %xmm0, %xmm4 ; SSE41-NEXT: movdqa %xmm3, %xmm4
; SSE41-NEXT: pcmpgtd %xmm3, %xmm4 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE41-NEXT: pcmpgtd %xmm0, %xmm3
; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,2,2]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm4, %xmm0
; SSE41-NEXT: pand %xmm5, %xmm0 ; SSE41-NEXT: por %xmm3, %xmm0
; SSE41-NEXT: por %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE41-NEXT: movd %xmm2, %eax ; SSE41-NEXT: movd %xmm2, %eax
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: test_v2i32: ; AVX1-LABEL: test_v2i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
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; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v2i16: ; SSE41-LABEL: test_v2i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pxor %xmm1, %xmm1 ; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3],xmm0[4],xmm1[5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3],xmm0[4],xmm1[5,6,7]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE41-NEXT: pmovzxwq {{.*#+}} xmm2 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero ; SSE41-NEXT: pmovzxwq {{.*#+}} xmm2 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm1, %xmm3 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: por %xmm0, %xmm3 ; SSE41-NEXT: por %xmm3, %xmm0
; SSE41-NEXT: por %xmm2, %xmm0 ; SSE41-NEXT: por %xmm2, %xmm3
; SSE41-NEXT: movdqa %xmm0, %xmm4 ; SSE41-NEXT: movdqa %xmm3, %xmm4
; SSE41-NEXT: pcmpgtd %xmm3, %xmm4 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE41-NEXT: pcmpgtd %xmm0, %xmm3
; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,2,2]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm4, %xmm0
; SSE41-NEXT: pand %xmm5, %xmm0 ; SSE41-NEXT: por %xmm3, %xmm0
; SSE41-NEXT: por %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE41-NEXT: movd %xmm2, %eax ; SSE41-NEXT: movd %xmm2, %eax
; SSE41-NEXT: # kill: def $ax killed $ax killed $eax ; SSE41-NEXT: # kill: def $ax killed $ax killed $eax
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v2i16: ; AVX-LABEL: test_v2i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v2i8: ; SSE41-LABEL: test_v2i8:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE41-NEXT: pand {{.*}}(%rip), %xmm1 ; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
; SSE41-NEXT: pmovzxbq {{.*#+}} xmm2 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero ; SSE41-NEXT: pmovzxbq {{.*#+}} xmm2 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm1, %xmm3 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: por %xmm0, %xmm3 ; SSE41-NEXT: por %xmm3, %xmm0
; SSE41-NEXT: por %xmm2, %xmm0 ; SSE41-NEXT: por %xmm2, %xmm3
; SSE41-NEXT: movdqa %xmm0, %xmm4 ; SSE41-NEXT: movdqa %xmm3, %xmm4
; SSE41-NEXT: pcmpgtd %xmm3, %xmm4 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE41-NEXT: pcmpgtd %xmm0, %xmm3
; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,2,2]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm4, %xmm0
; SSE41-NEXT: pand %xmm5, %xmm0 ; SSE41-NEXT: por %xmm3, %xmm0
; SSE41-NEXT: por %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE41-NEXT: pextrb $0, %xmm2, %eax ; SSE41-NEXT: pextrb $0, %xmm2, %eax
; SSE41-NEXT: # kill: def $al killed $al killed $eax ; SSE41-NEXT: # kill: def $al killed $al killed $eax
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v2i8: ; AVX-LABEL: test_v2i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1 ; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
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