[X86] Add INSERT_SUBVECTOR to ComputeNumSignBits

[craig.topper]

Summary

This adds support for calculating sign bits of insert_subvector. I based it on the computeKnownBits.

My motivating case is propagating sign bits information across basic blocks on AVX targets. Working on reduced test case.

[RKSimon]

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

3719

auto *SubIdx

3722

Use same approach as CONCAT_VECTORS above:

Tmp = std::numeric_limits<unsigned>::max();
...
assert(Tmp <= VTBits && "Failed to determine minimum sign bits");

3739

Is it safe to use DemandedElts at least on Src?

3743

Add a break - even though its the last case in the switch

[craig.topper]

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

3739

Maybe, but in practice we probably don't have insert_subvector with non-constant or out of bounds elements so its not going to get used much. We don't pass the demanded mask on the equivalent path in computeKnownBits either.

3743

I'm going to drop the else around this since we returned in the earlier block.

[craig.topper]

Address review comments. Add test case.

[RKSimon]

LGTM - cheers

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

case ISD::EXTRACT_SUBVECTOR: {
     if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) {
       // Offset the demanded elts by the subvector index.
       uint64_t Idx = SubIdx->getZExtValue();
       APInt DemandedSrc = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
       return ComputeNumSignBits(Src, DemandedSrc, Depth + 1);
     }
     return ComputeNumSignBits(Src, Depth + 1);
   }
-  case ISD::CONCAT_VECTORS:
+  case ISD::CONCAT_VECTORS: {
     // Determine the minimum number of sign bits across all demanded
     // elts of the input vectors. Early out if the result is already 1.
     Tmp = std::numeric_limits<unsigned>::max();
     EVT SubVectorVT = Op.getOperand(0).getValueType();
     unsigned NumSubVectorElts = SubVectorVT.getVectorNumElements();
     unsigned NumSubVectors = Op.getNumOperands();
     for (unsigned i = 0; (i < NumSubVectors) && (Tmp > 1); ++i) {
       APInt DemandedSub = DemandedElts.lshr(i * NumSubVectorElts);
       DemandedSub = DemandedSub.trunc(NumSubVectorElts);
       if (!DemandedSub)
         continue;
       Tmp2 = ComputeNumSignBits(Op.getOperand(i), DemandedSub, Depth + 1);
       Tmp = std::min(Tmp, Tmp2);
     }
     assert(Tmp <= VTBits && "Failed to determine minimum sign bits");
     return Tmp;
   }
+  case ISD::INSERT_SUBVECTOR: {
+    // If we know the element index, demand any elements from the subvector and
+    // the remainder from the src its inserted into, otherwise demand them all.
+    SDValue Src = Op.getOperand(0);
+    SDValue Sub = Op.getOperand(1);
+    ConstantSDNode *SubIdx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+    unsigned NumSubElts = Sub.getValueType().getVectorNumElements();
+    if (SubIdx && SubIdx->getAPIntValue().ule(NumElts - NumSubElts)) {
+      Tmp = Op.getValueSizeInBits();
+      uint64_t Idx = SubIdx->getZExtValue();
+      APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx);
+      if (!!DemandedSubElts) {
+        Tmp = ComputeNumSignBits(Sub, DemandedSubElts, Depth + 1);
+        if (Tmp == 1) return 1; // early-out
+      }
+      APInt SubMask = APInt::getBitsSet(NumElts, Idx, Idx + NumSubElts);
+      APInt DemandedSrcElts = DemandedElts & ~SubMask;
+      if (!!DemandedSrcElts) {
+        Tmp2 = ComputeNumSignBits(Src, DemandedSrcElts, Depth + 1);
+        Tmp = std::min(Tmp, Tmp2);
+      }
+      return Tmp;
+    } else {
+      Tmp = ComputeNumSignBits(Sub, Depth + 1);
+      if (Tmp == 1) return 1; // early-out
+      Tmp2 = ComputeNumSignBits(Src, Depth + 1);
+      Tmp = std::min(Tmp, Tmp2);
+      return Tmp;
+    }
+  }
+  }
 
   // If we are looking at the loaded value of the SDNode.
   if (Op.getResNo() == 0) {
     // Handle LOADX separately here. EXTLOAD case will fallthrough.
     if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
       unsigned ExtType = LD->getExtensionType();
       switch (ExtType) {
         default: break;