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[X86] Support SHLD/SHRD masked shift-counts (PR34641)
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Authored by RKSimon on Wed, Jan 2, 4:24 AM.

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Summary

Peek through shift modulo masks while matching double shift patterns.

I was hoping to delay this until I could remove the X86 code with generic funnel shift matching (PR40081) but this will do for now.

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Repository
rL LLVM

Event Timeline

RKSimon created this revision.Wed, Jan 2, 4:24 AM
spatel accepted this revision.Wed, Jan 2, 7:45 AM

LGTM

lib/Target/X86/X86ISelLowering.cpp
36543–36545 ↗(On Diff #179833)

Matter of taste, but we could avoid the partial-braces/indenting with something like:

if (ShAmt0.getOpcode() == ISD::AND &&
    isa<ConstantSDNode>(ShAmt0.getOperand(1)) &&
    ShAmt0.getConstantOperandVal(1) == Bits - 1)
This revision is now accepted and ready to land.Wed, Jan 2, 7:45 AM
This revision was automatically updated to reflect the committed changes.