[SelectionDAG] Teach BaseIndexOffset::match to unwrap the base after looking through an add/or

[craig.topper]

Summary

We might find a target specific node that needs to be unwrapped after we look through an add/or. Otherwise we get inconsistent results if one pointer is just X86WrapperRIP and the other is (add X86WrapperRIP, C)

The test that changed hasn't been commited yet. I'll commit if/when this patch is approved.

[niravd]

LGTM.

lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp

BaseIndexOffset BaseIndexOffset::match(const LSBaseSDNode *N,
   // Consume constant adds & ors with appropriate masking.
   while (true) {
     switch (Base->getOpcode()) {
     case ISD::OR:
       // Only consider ORs which act as adds.
       if (auto *C = dyn_cast<ConstantSDNode>(Base->getOperand(1)))
         if (DAG.MaskedValueIsZero(Base->getOperand(0), C->getAPIntValue())) {
           Offset += C->getSExtValue();
-          Base = Base->getOperand(0);
+          Base = DAG.getTargetLoweringInfo().unwrapAddress(Base->getOperand(0));
           continue;
         }
       break;
     case ISD::ADD:
       if (auto *C = dyn_cast<ConstantSDNode>(Base->getOperand(1))) {
         Offset += C->getSExtValue();
-        Base = Base->getOperand(0);
+        Base = DAG.getTargetLoweringInfo().unwrapAddress(Base->getOperand(0));
         continue;
       }
       break;
     case ISD::LOAD:
     case ISD::STORE: {
       auto *LSBase = cast<LSBaseSDNode>(Base.getNode());
       unsigned int IndexResNo = (Base->getOpcode() == ISD::LOAD) ? 1 : 0;
       if (LSBase->isIndexed() && Base.getResNo() == IndexResNo)
         if (auto *C = dyn_cast<ConstantSDNode>(LSBase->getOffset())) {
           auto Off = C->getSExtValue();
           if (LSBase->getAddressingMode() == ISD::PRE_DEC ||
               LSBase->getAddressingMode() == ISD::POST_DEC)
             Offset -= Off;
           else
             Offset += Off;
-          Base = LSBase->getBasePtr();
+          Base = DAG.getTargetLoweringInfo().unwrapAddress(LSBase->getBasePtr());
           continue;
         }
       break;
     }
     }
     // If we get here break out of the loop.
     break;
   }

test/CodeGen/X86/consecutive-load-shuffle.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-pc-windows | FileCheck %s
 
 ; We should be able to prodcue a single 128-bit load for these two 64-bit loads.
 ; But we previously weren't because we weren't consistently looking through
 ; WrapperRIP.
 
 @f = local_unnamed_addr global [4 x float] zeroinitializer, align 16
 @ms = common local_unnamed_addr global <4 x float> zeroinitializer, align 16
 
 define void @foo2() {
 ; CHECK-LABEL: foo2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT:    movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
-; CHECK-NEXT:    movapd %xmm0, {{.*}}(%rip)
+; CHECK-NEXT:    movaps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    movaps %xmm0, {{.*}}(%rip)
 ; CHECK-NEXT:    retq
 entry:
   %0 = load <2 x float>, <2 x float>* bitcast (float* getelementptr inbounds ([4 x float], [4 x float]* @f, i64 0, i64 2) to <2 x float>*), align 8
   %shuffle.i10 = shufflevector <2 x float> %0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   %1 = load <2 x float>, <2 x float>* bitcast ([4 x float]* @f to <2 x float>*), align 16
   %shuffle.i7 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   %shuffle.i = shufflevector <4 x float> %shuffle.i7, <4 x float> %shuffle.i10, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
   store <4 x float> %shuffle.i, <4 x float>* @ms, align 16
   ret void
 }