[Thumb2] ldrexd and strexd are not defined on v7M

[olista01]

Summary

The Thumb2 ldrexd and strexd instructions are not defined for M-class architectures.

[jroelofs]

I think compiler_rt's sync_fetch_and_*_8.S builtins will need some attention because of this.

[rengolin]

Hi Oliver,

Patch looks good. Thanks!

Can you do the change Jon proposed and submit another review?

cheers,
--renato

lib/Target/ARM/ARMInstrThumb2.td

3313

I thought IsThumb2 was already implied by being T2I_*. Anyway, looks ok.

[olista01]

Thanks, committed as revision 218603.

lib/Target/ARM/ARMInstrThumb2.td

def t2LDREX  : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
   let Inst{11-8} = 0b1111;
   let Inst{7-0} = addr{7-0};
 }
 let hasExtraDefRegAllocReq = 1 in
 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
                          (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldrexd", "\t$Rt, $Rt2, $addr", "",
-                         [], {?, ?, ?, ?}> {
+                         [], {?, ?, ?, ?}>,
+               Requires<[IsThumb2, IsNotMClass]> {
   bits<4> Rt2;
   let Inst{11-8} = Rt2;
 }
 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldaexb", "\t$Rt, $addr", "",
                          [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>,
                Requires<[IsThumb, HasV8]>;
def t2STREX  : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
   let Inst{11-8}  = Rd;
   let Inst{7-0} = addr{7-0};
 }
 let hasExtraSrcRegAllocReq = 1 in
 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
                          (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
-                         {?, ?, ?, ?}> {
+                         {?, ?, ?, ?}>,
+               Requires<[IsThumb2, IsNotMClass]> {
   bits<4> Rt2;
   let Inst{11-8} = Rt2;
 }
 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
                          (ins rGPR:$Rt, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "stlexb", "\t$Rd, $Rt, $addr", "",
                          [(set rGPR:$Rd,

test/MC/ARM/thumb2-ldrexd-strexd.s

+@ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s | FileCheck %s
+@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
+
+  ldrexd r0, r1, [r2]
+  strexd r3, r4, r5, [r6]
+
+@ CHECK: ldrexd r0, r1, [r2]            @ encoding: [0xd2,0xe8,0x7f,0x01]
+@ CHECK: strexd r3, r4, r5, [r6]        @ encoding: [0xc6,0xe8,0x73,0x45]
+
+@ UNDEF: error: instruction requires: !armv*m
+@ UNDEF: error: instruction requires: !armv*m