[X86] Allow pmulh to be formed from narrow vXi16 vectors under -x86-experimental-vector-widening-legalization

[craig.topper]

Summary

Narrower vectors will be widened to 128 bits without changing the element size. And generic type legalization can already handle widening mulhu/mulhs.

[spatel]

LGTM

lib/Target/X86/X86ISelLowering.cpp

static SDValue combinePMULH(SDValue Src, EVT VT, const SDLoc &DL,
   // First instruction should be a right shift of a multiply.
   if (Src.getOpcode() != ISD::SRL ||
       Src.getOperand(0).getOpcode() != ISD::MUL)
     return SDValue();
 
   if (!Subtarget.hasSSE2())
     return SDValue();
 
-  // Only handle vXi16 types that are at least 128-bits.
+  // Only handle vXi16 types that are at least 128-bits unless they will be
+  // widened.
   if (!VT.isVector() || VT.getVectorElementType() != MVT::i16 ||
-      VT.getVectorNumElements() < 8)
+      (!ExperimentalVectorWideningLegalization &&
+       VT.getVectorNumElements() < 8))
     return SDValue();
 
   // Input type should be vXi32.
   EVT InVT = Src.getValueType();
   if (InVT.getVectorElementType() != MVT::i32)
     return SDValue();
 
   // Need a shift by 16.

test/CodeGen/X86/pmulh.ll

 ; SSE2-PROMOTE-NEXT:    pmulhuw %xmm1, %xmm0
 ; SSE2-PROMOTE-NEXT:    pxor %xmm1, %xmm1
 ; SSE2-PROMOTE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; SSE2-PROMOTE-NEXT:    retq
 ;
 ; SSE2-WIDEN-LABEL: mulhuw_v4i16:
 ; SSE2-WIDEN:       # %bb.0:
 ; SSE2-WIDEN-NEXT:    pmulhuw %xmm1, %xmm0
-; SSE2-WIDEN-NEXT:    pxor %xmm1, %xmm1
-; SSE2-WIDEN-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE2-WIDEN-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
-; SSE2-WIDEN-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
-; SSE2-WIDEN-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
 ; SSE2-WIDEN-NEXT:    retq
 ;
 ; SSE41-PROMOTE-LABEL: mulhuw_v4i16:
 ; SSE41-PROMOTE:       # %bb.0:
 ; SSE41-PROMOTE-NEXT:    pxor %xmm2, %xmm2
 ; SSE41-PROMOTE-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7]
 ; SSE41-PROMOTE-NEXT:    pblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
 ; SSE41-PROMOTE-NEXT:    pmulld %xmm1, %xmm0
 ; SSE41-PROMOTE-NEXT:    psrld $16, %xmm0
 ; SSE41-PROMOTE-NEXT:    retq
 ;
 ; SSE41-WIDEN-LABEL: mulhuw_v4i16:
 ; SSE41-WIDEN:       # %bb.0:
-; SSE41-WIDEN-NEXT:    pmovzxwd {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; SSE41-WIDEN-NEXT:    pmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
-; SSE41-WIDEN-NEXT:    pmulld %xmm2, %xmm0
-; SSE41-WIDEN-NEXT:    psrld $16, %xmm0
-; SSE41-WIDEN-NEXT:    packusdw %xmm0, %xmm0
+; SSE41-WIDEN-NEXT:    pmulhuw %xmm1, %xmm0
 ; SSE41-WIDEN-NEXT:    retq
 ;
 ; AVX-LABEL: mulhuw_v4i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpxor %xmm2, %xmm2, %xmm2
 ; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7]
 ; AVX-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
 ; AVX-NEXT:    vpmulld %xmm1, %xmm0, %xmm0

 ; SSE2-PROMOTE-NEXT:    pmulhw %xmm1, %xmm0
 ; SSE2-PROMOTE-NEXT:    pxor %xmm1, %xmm1
 ; SSE2-PROMOTE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; SSE2-PROMOTE-NEXT:    retq
 ;
 ; SSE2-WIDEN-LABEL: mulhw_v4i16:
 ; SSE2-WIDEN:       # %bb.0:
 ; SSE2-WIDEN-NEXT:    pmulhw %xmm1, %xmm0
-; SSE2-WIDEN-NEXT:    pxor %xmm1, %xmm1
-; SSE2-WIDEN-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
-; SSE2-WIDEN-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
-; SSE2-WIDEN-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
-; SSE2-WIDEN-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
 ; SSE2-WIDEN-NEXT:    retq
 ;
 ; SSE41-PROMOTE-LABEL: mulhw_v4i16:
 ; SSE41-PROMOTE:       # %bb.0:
 ; SSE41-PROMOTE-NEXT:    pslld $16, %xmm0
 ; SSE41-PROMOTE-NEXT:    psrad $16, %xmm0
 ; SSE41-PROMOTE-NEXT:    pslld $16, %xmm1
 ; SSE41-PROMOTE-NEXT:    psrad $16, %xmm1
 ; SSE41-PROMOTE-NEXT:    pmulld %xmm1, %xmm0
 ; SSE41-PROMOTE-NEXT:    psrld $16, %xmm0
 ; SSE41-PROMOTE-NEXT:    retq
 ;
 ; SSE41-WIDEN-LABEL: mulhw_v4i16:
 ; SSE41-WIDEN:       # %bb.0:
-; SSE41-WIDEN-NEXT:    pmovsxwd %xmm0, %xmm2
-; SSE41-WIDEN-NEXT:    pmovsxwd %xmm1, %xmm0
-; SSE41-WIDEN-NEXT:    pmulld %xmm2, %xmm0
-; SSE41-WIDEN-NEXT:    psrld $16, %xmm0
-; SSE41-WIDEN-NEXT:    packusdw %xmm0, %xmm0
+; SSE41-WIDEN-NEXT:    pmulhw %xmm1, %xmm0
 ; SSE41-WIDEN-NEXT:    retq
 ;
 ; AVX-LABEL: mulhw_v4i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpslld $16, %xmm0, %xmm0
 ; AVX-NEXT:    vpsrad $16, %xmm0, %xmm0
 ; AVX-NEXT:    vpslld $16, %xmm1, %xmm1
 ; AVX-NEXT:    vpsrad $16, %xmm1, %xmm1