[RISCV] Add UNIMP instruction (32- and 16-bit forms)

[luismarques]

Summary

The UNIMP instruction isn't at the moment documented in the RISC-V ISA manual, but it's a GNU binutils de facto standard
for an instruction that's known not to be implemented, as thus one which will generate a trap, assuming your system generates such traps at all.

This patch adds support for UNIMP in both 32- and 16-bit forms. The 32-bit form can be seen as a variant of the ECALL/EBREAK/etc. family of instructions. The 16-bit form is just all zeroes, which isn't a valid RISC-V instruction, but still follows the 16-bit instruction form (i.e. bits 0-1 != 11).

[asb]

I think this is fine, but c.unimp should be proposed on the RISC-V sw-dev mailing list or similar. As we discussed, it seems to make total sense to have this instruction (every other compressed instruction is nameable with c.something). But we should get community feedback first before merging in to LLVM. It's probably also worth highlighting the fact that "unimp" isn't actually guaranteed to trap according to the current RISC-V specs...

So that's a LGTM, but blocked on external discussion. Thanks!

[asb]

Thanks to Luís, there is agreement on c.unimp on the sw-dev mailing list, it's now documented in the RISC-V asm manual, and binutils now supports c.unimp too (courtesy of Jim Wilson).

Therefore, this is good to land. Many thanks!

llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td

def ECALL : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ecall", ""> {
   let imm12 = 0;
 }
 
 def EBREAK : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ebreak", ""> {
   let rs1 = 0;
   let rd = 0;
   let imm12 = 1;
 }
+
+// This is a de facto standard (as set by GNU binutils) 32-bit unimplemented
+// instruction (i.e., it should always trap, if your implementation has invalid
+// instruction traps).
+def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", ""> {
+  let rs1 = 0;
+  let rd = 0;
+  let imm12 = 0b110000000000;
+}
 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
 
 def CSRRW : CSR_ir<0b001, "csrrw">;
 def CSRRS : CSR_ir<0b010, "csrrs">;
 def CSRRC : CSR_ir<0b011, "csrrc">;
 
 def CSRRWI : CSR_ii<0b101, "csrrwi">;
 def CSRRSI : CSR_ii<0b110, "csrrsi">;

llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td

 }
 
 let Predicates = [HasStdExtC, IsRV64] in
 def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000> {
   let Inst{12-10} = imm{5-3};
   let Inst{9-7}   = imm{8-6};
 }
 
+// The all zeros pattern isn't a valid RISC-V instruction. It's used by GNU
+// binutils as 16-bit instruction known to be unimplemented (i.e., trapping).
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther> {
+  let Inst{15-0} = 0;
+}
+
 } // Predicates = [HasStdExtC]
 
 //===----------------------------------------------------------------------===//
 // Compress Instruction tablegen backend.
 //===----------------------------------------------------------------------===//
 
 class CompressPat<dag input, dag output> {
   dag Input  = input;
def : CompressPat<(JALR X0, GPRNoX0:$rs1, 0),
                   (C_JR GPRNoX0:$rs1)>;
 def : CompressPat<(ADD GPRNoX0:$rs1, X0, GPRNoX0:$rs2),
                   (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
 def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, X0),
                   (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
                   (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
 def : CompressPat<(EBREAK), (C_EBREAK)>;
+def : CompressPat<(UNIMP), (C_UNIMP)>;
 def : CompressPat<(JALR X1, GPRNoX0:$rs1, 0),
                   (C_JALR GPRNoX0:$rs1)>;
 def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
                   (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
 def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs1),
                   (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
 } // Predicates = [HasStdExtC]
 

llvm/trunk/test/MC/RISCV/compress-rv32i.s

 # CHECK: # encoding:  [0x3e,0x94]
 add s0, s0, a5
 
 # CHECK-BYTES: 82 df
 # CHECK-ALIAS: sw zero, 252(sp)
 # CHECK-INST: c.swsp zero, 252(sp)
 # CHECK: # encoding: [0x82,0xdf]
 sw zero, 252(sp)
+
+# CHECK-BYTES: 00 00
+# CHECK-ALIAS: unimp
+# CHECK-INST: c.unimp
+# CHECK: # encoding: [0x00,0x00]
+unimp

llvm/trunk/test/MC/RISCV/rv32c-valid.s

 # CHECK-ASM: encoding: [0x7d,0x64]
 c.lui s0, 31
 # CHECK-ASM-AND-OBJ: c.lui s0, 1048544
 # CHECK-ASM: encoding: [0x01,0x74]
 c.lui s0, 0xfffe0
 # CHECK-ASM-AND-OBJ: c.lui s0, 1048575
 # CHECK-ASM: encoding: [0x7d,0x74]
 c.lui s0, 0xfffff
+# CHECK-ASM-AND-OBJ: c.unimp
+# CHECK-ASM: encoding: [0x00,0x00]
+c.unimp

llvm/trunk/test/MC/RISCV/rv32i-valid.s

 fence.i
 
 # CHECK-ASM-AND-OBJ: ecall
 # CHECK-ASM: encoding: [0x73,0x00,0x00,0x00]
 ecall
 # CHECK-ASM-AND-OBJ: ebreak
 # CHECK-ASM: encoding: [0x73,0x00,0x10,0x00]
 ebreak
+# CHECK-ASM-AND-OBJ: unimp
+# CHECK-ASM: encoding: [0x73,0x10,0x00,0xc0]
+unimp
 
 # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
 # CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff]
 csrrw t0, 0xfff, t1
 # CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
 # CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0]
 csrrs s0, 0xc00, x0
 # CHECK-ASM-AND-OBJ: csrrs s3, 1, s5