This is an archive of the discontinued LLVM Phabricator instance.

[MSP430] Fix encodeInstruction() for big endian hosts
ClosedPublic

Authored by mskvortsov on Nov 8 2018, 2:16 AM.

Reviewers

Commits

Repository

rL LLVM

Build Status

Buildable 24724
Build 24723: arc lint + arc unit

This revision was not accepted when it landed; it landed in state Needs Review.Nov 8 2018, 2:20 AM

This revision was automatically updated to reflect the committed changes.

Thanks. Committed as r346391

Path

Size

lib/

Target/

MSP430/

MCTargetDesc/

7 lines

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines	void MSP430MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());		const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
// Get byte count of instruction.		// Get byte count of instruction.
unsigned Size = Desc.getSize();		unsigned Size = Desc.getSize();

// Initialize fixup offset		// Initialize fixup offset
Offset = 2;		Offset = 2;

uint64_t BinaryOpCode = getBinaryCodeForInstr(MI, Fixups, STI);		uint64_t BinaryOpCode = getBinaryCodeForInstr(MI, Fixups, STI);
const uint16_t Words = reinterpret_cast<uint16_t const >(&BinaryOpCode);
size_t WordCount = Size / 2;		size_t WordCount = Size / 2;

for (size_t i = 0; i < WordCount; ++i) {		while (WordCount--) {
uint16_t Word = Words[i];		support::endian::write(OS, (uint16_t)BinaryOpCode, support::little);
support::endian::write(OS, Word, support::little);		BinaryOpCode >>= 16;
}		}
}		}

unsigned MSP430MCCodeEmitter::getMachineOpValue(const MCInst &MI,		unsigned MSP430MCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO,		const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,		SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {		const MCSubtargetInfo &STI) const {
if (MO.isReg())		if (MO.isReg())
▲ Show 20 Lines • Show All 105 Lines • Show Last 20 Lines