[Power] Use lwsync for non-seq_cst fences

[morisset]

Summary

hwsync is only required for seq_cst fences, acquire and release one can use
the cheaper lwsync.

[morisset]

Rebase on trunk.

[hfinkel]

LGTM.

Please add a test run with ppc440 to make sure we still get msync.

lib/Target/PowerPC/PPCInstrInfo.td

2559

By the way, what happens to AtomicOrdering == 2 (which is Monotonic). Is that (should that be) a noop?

[morisset]

I will add the test with ppc440.

This path is only for fences, and I do not think a monotonic fence makes
much sense. So it is not special cased (but should trigger a bunch of
errors earlier in the front-end or at least asserts in the middle-end).

Thanks for the reviews !

[morisset]

Closed by commit rL218995 (authored by @morisset).

lib/Target/PowerPC/PPCInstrInfo.td

 def : Pat<(f64 (extloadf32 iaddr:$src)),
           (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
 def : Pat<(f64 (extloadf32 xaddr:$src)),
           (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
 
 def : Pat<(f64 (fextend f32:$src)),
           (COPY_TO_REGCLASS $src, F8RC)>;
 
-def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
+// Only seq_cst fences require the heavyweight sync (SYNC 0).
+// All others can use the lightweight sync (SYNC 1).
+// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
+// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
+// versions of Power.
+def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
+def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
+def : Pat<(atomic_fence (imm),   (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
 
 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
           (FNMSUB $A, $C, $B)>;
 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
           (FNMSUB $A, $C, $B)>;
 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),

test/CodeGen/PowerPC/atomics.ll

 }
 define i64 @and_i64_release(i64* %mem, i64 %operand) {
 ; CHECK-LABEL: and_i64_release
 ; CHECK: sync 1
   %val = atomicrmw and i64* %mem, i64 %operand release
 ; CHECK-NOT: [sync ]
   ret i64 %val
 }
+
+; Fences
+define void @fence_acquire() {
+; CHECK-LABEL: fence_acquire
+; CHECK: sync 1
+  fence acquire
+  ret void
+}
+define void @fence_release() {
+; CHECK-LABEL: fence_release
+; CHECK: sync 1
+  fence release
+  ret void
+}
+define void @fence_seq_cst() {
+; CHECK-LABEL: fence_seq_cst
+; CHECK: sync 0
+  fence seq_cst
+  ret void
+}