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[X86] ALU/ADC RMW instructions should use the WriteRMW sequence class
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Authored by RKSimon on Oct 1 2018, 11:55 AM.

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Summary

I was expecting this to be a nfc but Silvermont seems to be setup a little differently:

A folded store needs a cycle on MEC_RSV for the store data, but it does not
need an extra port cycle to recompute the address.
def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;

So moving from WriteStore to WriteRMW reduces predicted port pressure. From what I can tell this is correct but I wanted to confirm with some Intel guys as my knowledge of SLM is very weak.

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RKSimon created this revision.Oct 1 2018, 11:55 AM

I think this is right, but I've got an email out to the Atom team internally to confirm.

This revision is now accepted and ready to land.Oct 2 2018, 5:31 PM
This revision was automatically updated to reflect the committed changes.