Page MenuHomePhabricator

[IAI,LV] Avoid creating interleave-groups for predicated accesses
ClosedPublic

Authored by dorit on Sep 28 2018, 10:31 PM.

Details

Summary

This patch fixes PR39099.

When strided loads are predicated, each of them will form an interleaved-group (with gaps). However, subsequent stages of vectorization (planning and transformation) assume that if a load is part of an Interleave-Group it is not predicated, resulting in wrong code - unmasked wide loads are created.

The Interleaving Analysis does take care not to have conditional interleave groups of size > 1, but until we extend the planning and transformation stages to support masked-interleave-groups (I have a patch coming up for that), we should also avoid having them for size == 1.

Diff Detail

Repository
rL LLVM

Event Timeline

dorit created this revision.Sep 28 2018, 10:31 PM
Ayal accepted this revision.Oct 2 2018, 6:53 AM

Nice catch, added only minor optional comments.

lib/Analysis/VectorUtils.cpp
715 ↗(On Diff #167581)

Best add TODO when referring to such potential "in the future" work.

815 ↗(On Diff #167581)

This check for isPredicated(B) now becomes redundant, right?

test/Transforms/LoopVectorize/X86/x86-pr39099.ll
9 ↗(On Diff #167581)

CHECK for three scalarized accesse below, as claimed above. Alternatively, stores with gaps are (currently) not supported, so the bug is relevant for loads only; i.e, suffice to test with consecutive stores to q[ix].

This revision is now accepted and ready to land.Oct 2 2018, 6:53 AM
dorit marked 2 inline comments as done.Oct 6 2018, 11:56 PM

Thanks!

lib/Analysis/VectorUtils.cpp
815 ↗(On Diff #167581)

Actually not, because the code after this check assumes that B has a Group…

This revision was automatically updated to reflect the committed changes.