[ARM] Allow execute only code on Cortex-m23

[DavidSpickett]

Summary

The NoMovt feature prevents the use of MOVW/MOVT instructions on Cortex-M23 for performance reasons.
These instructions are required for execute only code so NoMovt should be disabled when that option is enabled.

[javed.absar]

Looks like you forgot to add context (git diff -U9999)

[DavidSpickett]

Added diff context.

llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   }
   ParseSubtargetFeatures(CPUString, ArchFS);
 
   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
   // Assert this for now to make the change obvious.
   assert(hasV6T2Ops() || !hasThumb2());
 
   // Execute only support requires movt support
-  if (genExecuteOnly())
-    assert(hasV8MBaselineOps() && !NoMovt && "Cannot generate execute-only code for this target");
+  if (genExecuteOnly()) {
+    NoMovt = false;
+    assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
+  }
 
   // Keep a pointer to static instruction cost data for the specified CPU.
   SchedModel = getSchedModelForCPU(CPUString);
 
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUString);
 
   // FIXME: this is invalid for WindowsCE

llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll

 ; RUN: llc < %s -mtriple=thumbv7m -mattr=+execute-only -O0 %s -o - \
 ; RUN:  | FileCheck --check-prefix=CHECK-SUBW-ADDW %s
 ; RUN: llc < %s -mtriple=thumbv8m.base -mattr=+execute-only -O0 %s -o - \
 ; RUN:  | FileCheck --check-prefix=CHECK-MOVW-MOVT-ADD %s
+; RUN: llc < %s -mtriple=thumbv8m.base -mcpu=cortex-m23 -mattr=+execute-only -O0 %s -o - \
+; RUN:  | FileCheck --check-prefix=CHECK-MOVW-MOVT-ADD %s
 ; RUN: llc < %s -mtriple=thumbv8m.main -mattr=+execute-only -O0 %s -o - \
 ; RUN:  | FileCheck --check-prefix=CHECK-SUBW-ADDW %s
 
 define i8 @test_big_stack_frame() {
 ; CHECK-SUBW-ADDW-LABEL: test_big_stack_frame:
 ; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
 ; CHECK-SUBW-ADDW:       sub.w sp, sp, #65536
 ; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}

llvm/trunk/test/CodeGen/ARM/execute-only-section.ll

 ; RUN: llc < %s -mtriple=thumbv7m -mattr=+execute-only %s -o - | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv8m.base -mattr=+execute-only %s -o - | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv8m.base -mcpu=cortex-m23 -mattr=+execute-only %s -o - | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv8m.main -mattr=+execute-only %s -o - | FileCheck %s
 
 ; CHECK:     .section .text,"axy",%progbits,unique,0
 ; CHECK-NOT: .section
 ; CHECK-NOT: .text
 ; CHECK:     .globl test_SectionForGlobal
 ; CHECK:     .type test_SectionForGlobal,%function
 define void @test_SectionForGlobal() {

llvm/trunk/test/CodeGen/ARM/execute-only.ll

 ; RUN: llc -mtriple=thumbv8m.base-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
+; RUN: llc -mtriple=thumbv8m.base-eabi -mcpu=cortex-m23 -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
 ; RUN: llc -mtriple=thumbv7m-eabi      -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
 ; RUN: llc -mtriple=thumbv8m.main-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
 
 ; CHECK-NOT: {{^ *}}.text{{$}}
 ; CHECK: .section .text,"axy",%progbits,unique,0
 
 @var = global i32 0