[ARM] Fix FixConsts for ARMCodeGenPrepare

[samparker]

Summary

Part of FixConsts wrongly assumes either a 8- or 16-bit constant which can result in the wrong constants being generated during promotion.

[SjoerdMeijer]

Lgtm

llvm/trunk/lib/Target/ARM/ARMCodeGenPrepare.cpp

bool IsDecreasing = ((Opc == Instruction::Sub) && !NegImm) ||
                         ((Opc == Instruction::Add) && NegImm);
     if (!IsDecreasing)
       return false;
 
     LLVM_DEBUG(dbgs() << "ARM CGP: Allowing safe overflow for " << *I << "\n");
     return true;
   }
 
-  // Otherwise, if an instruction is using a negative immediate we will need
-  // to fix it up during the promotion.
-  for (auto &Op : I->operands()) {
-    if (auto *Const = dyn_cast<ConstantInt>(Op))
-      if (Const->isNegative())
-        return false;
-  }
   return false;
 }
 
 static bool shouldPromote(Value *V) {
   if (!isa<IntegerType>(V->getType()) || isSink(V)) {
     LLVM_DEBUG(dbgs() << "ARM CGP: Don't need to promote: " << *V << "\n");
     return false;
   }
for (Use &U : From->uses()) {
       Users.push_back(User);
     }
 
     for (auto &U : Users)
       U->replaceUsesOfWith(From, To);
   };
 
   auto FixConst = [&](ConstantInt *Const, Instruction *I) {
-    Constant *NewConst = nullptr;
-    if (isSafeOverflow(I)) {
-      NewConst = (Const->isNegative()) ?
-        ConstantExpr::getSExt(Const, ExtTy) :
-        ConstantExpr::getZExt(Const, ExtTy);
-    } else {
-      uint64_t NewVal = *Const->getValue().getRawData();
-      if (Const->getType() == Type::getInt16Ty(Ctx))
-        NewVal &= 0xFFFF;
-      else
-        NewVal &= 0xFF;
-      NewConst = ConstantInt::get(ExtTy, NewVal);
-    }
+    Constant *NewConst = isSafeOverflow(I) && Const->isNegative() ?
     I->replaceUsesOfWith(Const, NewConst);
   };
 
   auto InsertDSPIntrinsic = [&](Instruction *I) {
     LLVM_DEBUG(dbgs() << "ARM CGP: Inserting DSP intrinsic for "
                << *I << "\n");
     Function *DSPInst =
       Intrinsic::getDeclaration(M, getNarrowIntrinsic(I));

llvm/trunk/test/CodeGen/ARM/arm-cgp-icmps.ll

-; RUN: llc -mtriple=thumbv8.main -mcpu=cortex-m33 %s -arm-disable-cgp=false -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-NODSP
+; RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 %s -arm-disable-cgp=false -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-NODSP
 ; RUN: llc -mtriple=thumbv7em %s -arm-disable-cgp=false -arm-enable-scalar-dsp=true -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-DSP
 ; RUN: llc -mtriple=thumbv8 %s -arm-disable-cgp=false -arm-enable-scalar-dsp=true -arm-enable-scalar-dsp-imms=true -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-DSP-IMM
 
 ; CHECK-COMMON-LABEL: test_ult_254_inc_imm:
 ; CHECK-DSP:        adds    r0, #1
 ; CHECK-DSP-NEXT:   uxtb    r1, r0
 ; CHECK-DSP-NEXT:   movs    r0, #47
 ; CHECK-DSP-NEXT:   cmp     r1, #254

 entry:
   %load = load i7, i7* %arg0
   %add = add nuw i7 %load, 1
   %cmp = icmp ult i7 %arg1, %add
   %res = select i1 %cmp, i32 %a, i32 %b
   ret i32 %res
 }
 
+; CHECK-COMMON-LABEL: icmp_i15
+; CHECK-COMMON: movw [[MINUS_ONE:r[0-9]+]], #32767
+define i32 @icmp_i15(i15 zeroext %arg0, i15 zeroext %arg1) {
+  %xor = xor i15 %arg0, -1
+  %cmp = icmp eq i15 %xor, %arg1
+  %res = select i1 %cmp, i32 21, i32 42
+  ret i32 %res
+}
+