[X86] Remove isel patterns for ADCX instruction

[craig.topper]

Summary

There's no advantage to this instruction unless you need to avoid touching other flag bits. It's encoding is longer, it can't fold an immediate, it doesn't write all the flags.

I don't think gcc will generate this instruction either.

Fixes PR38852.

[RKSimon]

We losing a lot of test coverage of the ADX instructions here - we already don't have any ADOX test coverage other than with inline asm.

Plus I don't think SBB is an ADX instruction?

[craig.topper]

Rebase after the other ADC changes that have gone in recently. Add a non-ADX command line to the stack folding test.

I've added a commuting and stack folding MIR test for the ADCX and ADOX instructions since we can't isel them.

[RKSimon]

LGTM

llvm/trunk/lib/Target/X86/X86InstrArithmetic.td

let Uses = [EDX] in
     defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, WriteIMul>;
   let Uses = [RDX] in
     defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteIMul64>, VEX_W;
 }
 
 //===----------------------------------------------------------------------===//
 // ADCX and ADOX Instructions
 //
+// We don't have patterns for these as there is no advantage over ADC for
+// most code.
 let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS],
-    Constraints = "$src1 = $dst", AddedComplexity = 10 in {
+    Constraints = "$src1 = $dst", hasSideEffects = 0 in {
   let SchedRW = [WriteADC], isCommutable = 1 in {
   def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst),
                    (ins GR32:$src1, GR32:$src2),
-                   "adcx{l}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR32:$dst, EFLAGS,
-                     (X86adc_flag GR32:$src1, GR32:$src2, EFLAGS))]>, T8PD;
+                   "adcx{l}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
   def ADCX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst),
                     (ins GR64:$src1, GR64:$src2),
-                    "adcx{q}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR64:$dst, EFLAGS,
-                      (X86adc_flag GR64:$src1, GR64:$src2, EFLAGS))]>, T8PD;
+                    "adcx{q}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
 
-  // We don't have patterns for ADOX yet.
-  let hasSideEffects = 0 in {
   def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst),
                    (ins GR32:$src1, GR32:$src2),
                    "adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
 
   def ADOX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst),
                     (ins GR64:$src1, GR64:$src2),
                     "adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
-  } // hasSideEffects = 0
   } // SchedRW
 
   let mayLoad = 1, SchedRW = [WriteADCLd, ReadAfterLd] in {
   def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst),
                    (ins GR32:$src1, i32mem:$src2),
-                   "adcx{l}\t{$src2, $dst|$dst, $src2}",
-                   [(set GR32:$dst, EFLAGS,
-                     (X86adc_flag GR32:$src1, (loadi32 addr:$src2), EFLAGS))]>,
-                   T8PD;
+                   "adcx{l}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
 
   def ADCX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst),
                     (ins GR64:$src1, i64mem:$src2),
-                    "adcx{q}\t{$src2, $dst|$dst, $src2}",
-                    [(set GR64:$dst, EFLAGS,
-                      (X86adc_flag GR64:$src1, (loadi64 addr:$src2), EFLAGS))]>,
-                    T8PD;
+                    "adcx{q}\t{$src2, $dst|$dst, $src2}", []>, T8PD;
 
-  // We don't have patterns for ADOX yet.
-  let hasSideEffects = 0 in {
   def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst),
                    (ins GR32:$src1, i32mem:$src2),
                    "adox{l}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
 
   def ADOX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst),
                     (ins GR64:$src1, i64mem:$src2),
                     "adox{q}\t{$src2, $dst|$dst, $src2}", []>, T8XS;
-  } // hasSideEffects = 0
   } // mayLoad = 1, SchedRW = [WriteADCLd]
 }
-
-// Patterns to recognize loads on the LHS of an ADC. We can't make X86adc_flag
-// commutable since it has EFLAGs as an input.
-let Predicates = [HasADX], AddedComplexity = 10 in {
-  def : Pat<(X86adc_flag (loadi32 addr:$src2), GR32:$src1, EFLAGS),
-            (ADCX32rm GR32:$src1, addr:$src2)>;
-  def : Pat<(X86adc_flag (loadi64 addr:$src2), GR64:$src1, EFLAGS),
-            (ADCX64rm GR64:$src1, addr:$src2)>;
-}

llvm/trunk/test/CodeGen/X86/adx-intrinsics-upgrade.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 --show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=NOADX
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=broadwell --show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=ADX
 
 declare i8 @llvm.x86.addcarryx.u32(i8, i32, i32, i8*)
 
 define i8 @test_addcarryx_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarryx_u32:
-; NOADX:       ## %bb.0:
-; NOADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT:    adcl %edx, %esi ## encoding: [0x11,0xd6]
-; NOADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; NOADX-NEXT:    retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarryx_u32:
-; ADX:       ## %bb.0:
-; ADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT:    adcxl %edx, %esi ## encoding: [0x66,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; ADX-NEXT:    retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarryx_u32:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT:    adcl %edx, %esi ## encoding: [0x11,0xd6]
+; CHECK-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
+; CHECK-NEXT:    retq ## encoding: [0xc3]
   %ret = tail call i8 @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b, i8* %ptr)
   ret i8 %ret;
 }
 
 declare i8 @llvm.x86.addcarryx.u64(i8, i64, i64, i8*)
 
 define i8 @test_addcarryx_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarryx_u64:
-; NOADX:       ## %bb.0:
-; NOADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT:    adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
-; NOADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; NOADX-NEXT:    retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarryx_u64:
-; ADX:       ## %bb.0:
-; ADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT:    adcxq %rdx, %rsi ## encoding: [0x66,0x48,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; ADX-NEXT:    retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarryx_u64:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT:    adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
+; CHECK-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
+; CHECK-NEXT:    retq ## encoding: [0xc3]
   %ret = tail call i8 @llvm.x86.addcarryx.u64(i8 %c, i64 %a, i64 %b, i8* %ptr)
   ret i8 %ret;
 }
 
 declare i8 @llvm.x86.addcarry.u32(i8, i32, i32, i8*)
 
 define i8 @test_addcarry_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarry_u32:
-; NOADX:       ## %bb.0:
-; NOADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT:    adcl %edx, %esi ## encoding: [0x11,0xd6]
-; NOADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; NOADX-NEXT:    retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarry_u32:
-; ADX:       ## %bb.0:
-; ADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT:    adcxl %edx, %esi ## encoding: [0x66,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; ADX-NEXT:    retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarry_u32:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT:    adcl %edx, %esi ## encoding: [0x11,0xd6]
+; CHECK-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
+; CHECK-NEXT:    retq ## encoding: [0xc3]
   %ret = tail call i8 @llvm.x86.addcarry.u32(i8 %c, i32 %a, i32 %b, i8* %ptr)
   ret i8 %ret;
 }
 
 declare i8 @llvm.x86.addcarry.u64(i8, i64, i64, i8*)
 
 define i8 @test_addcarry_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarry_u64:
-; NOADX:       ## %bb.0:
-; NOADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT:    adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
-; NOADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; NOADX-NEXT:    retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarry_u64:
-; ADX:       ## %bb.0:
-; ADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT:    adcxq %rdx, %rsi ## encoding: [0x66,0x48,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; ADX-NEXT:    retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarry_u64:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT:    adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
+; CHECK-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
+; CHECK-NEXT:    retq ## encoding: [0xc3]
   %ret = tail call i8 @llvm.x86.addcarry.u64(i8 %c, i64 %a, i64 %b, i8* %ptr)
   ret i8 %ret;
 }
 
 declare i8 @llvm.x86.subborrow.u32(i8, i32, i32, i8*)
 
 define i8 @test_subborrow_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
 ; CHECK-LABEL: test_subborrow_u32:

 ; CHECK-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %ret = tail call i8 @llvm.x86.subborrow.u64(i8 %c, i64 %a, i64 %b, i8* %ptr)
   ret i8 %ret;
 }
 
 ; Try a version with loads. Previously we crashed on this.
 define i32 @load_crash(i64* nocapture readonly %a, i64* nocapture readonly %b, i64* %res)  {
-; NOADX-LABEL: load_crash:
-; NOADX:       ## %bb.0:
-; NOADX-NEXT:    movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
-; NOADX-NEXT:    xorl %ecx, %ecx ## encoding: [0x31,0xc9]
-; NOADX-NEXT:    addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
-; NOADX-NEXT:    adcq (%rsi), %rax ## encoding: [0x48,0x13,0x06]
-; NOADX-NEXT:    setb %cl ## encoding: [0x0f,0x92,0xc1]
-; NOADX-NEXT:    movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
-; NOADX-NEXT:    movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
-; NOADX-NEXT:    retq ## encoding: [0xc3]
-;
-; ADX-LABEL: load_crash:
-; ADX:       ## %bb.0:
-; ADX-NEXT:    movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
-; ADX-NEXT:    xorl %ecx, %ecx ## encoding: [0x31,0xc9]
-; ADX-NEXT:    addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
-; ADX-NEXT:    adcxq (%rsi), %rax ## encoding: [0x66,0x48,0x0f,0x38,0xf6,0x06]
-; ADX-NEXT:    setb %cl ## encoding: [0x0f,0x92,0xc1]
-; ADX-NEXT:    movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
-; ADX-NEXT:    movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
-; ADX-NEXT:    retq ## encoding: [0xc3]
+; CHECK-LABEL: load_crash:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
+; CHECK-NEXT:    xorl %ecx, %ecx ## encoding: [0x31,0xc9]
+; CHECK-NEXT:    addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
+; CHECK-NEXT:    adcq (%rsi), %rax ## encoding: [0x48,0x13,0x06]
+; CHECK-NEXT:    setb %cl ## encoding: [0x0f,0x92,0xc1]
+; CHECK-NEXT:    movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
+; CHECK-NEXT:    movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
+; CHECK-NEXT:    retq ## encoding: [0xc3]
   %1 = load i64, i64* %a, align 8
   %2 = load i64, i64* %b, align 8
   %3 = bitcast i64* %res to i8*
   %4 = tail call i8 @llvm.x86.addcarryx.u64(i8 0, i64 %1, i64 %2, i8* %3)
   %conv = zext i8 %4 to i32
   ret i32 %conv
 }
 

llvm/trunk/test/CodeGen/X86/adx-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 --show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=NOADX
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=broadwell --show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=ADX
 
 declare { i8, i32 } @llvm.x86.addcarryx.u32(i8, i32, i32)
 
 define i8 @test_addcarryx_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarryx_u32:
-; NOADX:       ## %bb.0:
-; NOADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT:    adcl %edx, %esi ## encoding: [0x11,0xd6]
-; NOADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; NOADX-NEXT:    retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarryx_u32:
-; ADX:       ## %bb.0:
-; ADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT:    adcxl %edx, %esi ## encoding: [0x66,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; ADX-NEXT:    retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarryx_u32:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT:    adcl %edx, %esi ## encoding: [0x11,0xd6]
+; CHECK-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
+; CHECK-NEXT:    retq ## encoding: [0xc3]
   %ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b)
   %1 = extractvalue { i8, i32 } %ret, 1
   %2 = bitcast i8* %ptr to i32*
   store i32 %1, i32* %2, align 1
   %3 = extractvalue { i8, i32 } %ret, 0
   ret i8 %3
 }
 
 define i8 @test_addcarryx_u32_load(i8 %c, i32* %aptr, i32 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarryx_u32_load:
-; NOADX:       ## %bb.0:
-; NOADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT:    adcl (%rsi), %edx ## encoding: [0x13,0x16]
-; NOADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT:    movl %edx, (%rcx) ## encoding: [0x89,0x11]
-; NOADX-NEXT:    retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarryx_u32_load:
-; ADX:       ## %bb.0:
-; ADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT:    adcxl (%rsi), %edx ## encoding: [0x66,0x0f,0x38,0xf6,0x16]
-; ADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT:    movl %edx, (%rcx) ## encoding: [0x89,0x11]
-; ADX-NEXT:    retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarryx_u32_load:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT:    adcl (%rsi), %edx ## encoding: [0x13,0x16]
+; CHECK-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT:    movl %edx, (%rcx) ## encoding: [0x89,0x11]
+; CHECK-NEXT:    retq ## encoding: [0xc3]
   %a = load i32, i32* %aptr
   %ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b)
   %1 = extractvalue { i8, i32 } %ret, 1
   %2 = bitcast i8* %ptr to i32*
   store i32 %1, i32* %2, align 1
   %3 = extractvalue { i8, i32 } %ret, 0
   ret i8 %3
 }
 
 define i8 @test_addcarryx_u32_load2(i8 %c, i32 %a, i32* %bptr, i8* %ptr) {
-; NOADX-LABEL: test_addcarryx_u32_load2:
-; NOADX:       ## %bb.0:
-; NOADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT:    adcl (%rdx), %esi ## encoding: [0x13,0x32]
-; NOADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; NOADX-NEXT:    retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarryx_u32_load2:
-; ADX:       ## %bb.0:
-; ADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT:    adcxl (%rdx), %esi ## encoding: [0x66,0x0f,0x38,0xf6,0x32]
-; ADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; ADX-NEXT:    retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarryx_u32_load2:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT:    adcl (%rdx), %esi ## encoding: [0x13,0x32]
+; CHECK-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
+; CHECK-NEXT:    retq ## encoding: [0xc3]
   %b = load i32, i32* %bptr
   %ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b)
   %1 = extractvalue { i8, i32 } %ret, 1
   %2 = bitcast i8* %ptr to i32*
   store i32 %1, i32* %2, align 1
   %3 = extractvalue { i8, i32 } %ret, 0
   ret i8 %3
 }
 
 declare { i8, i64 } @llvm.x86.addcarryx.u64(i8, i64, i64)
 
 define i8 @test_addcarryx_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarryx_u64:
-; NOADX:       ## %bb.0:
-; NOADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT:    adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
-; NOADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; NOADX-NEXT:    retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarryx_u64:
-; ADX:       ## %bb.0:
-; ADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT:    adcxq %rdx, %rsi ## encoding: [0x66,0x48,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; ADX-NEXT:    retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarryx_u64:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT:    adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
+; CHECK-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
+; CHECK-NEXT:    retq ## encoding: [0xc3]
   %ret = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 %c, i64 %a, i64 %b)
   %1 = extractvalue { i8, i64 } %ret, 1
   %2 = bitcast i8* %ptr to i64*
   store i64 %1, i64* %2, align 1
   %3 = extractvalue { i8, i64 } %ret, 0
   ret i8 %3
 }
 
 declare { i8, i32 } @llvm.x86.addcarry.u32(i8, i32, i32)
 
 define i8 @test_addcarry_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarry_u32:
-; NOADX:       ## %bb.0:
-; NOADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT:    adcl %edx, %esi ## encoding: [0x11,0xd6]
-; NOADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; NOADX-NEXT:    retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarry_u32:
-; ADX:       ## %bb.0:
-; ADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT:    adcxl %edx, %esi ## encoding: [0x66,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
-; ADX-NEXT:    retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarry_u32:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT:    adcl %edx, %esi ## encoding: [0x11,0xd6]
+; CHECK-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT:    movl %esi, (%rcx) ## encoding: [0x89,0x31]
+; CHECK-NEXT:    retq ## encoding: [0xc3]
   %ret = call { i8, i32 } @llvm.x86.addcarry.u32(i8 %c, i32 %a, i32 %b)
   %1 = extractvalue { i8, i32 } %ret, 1
   %2 = bitcast i8* %ptr to i32*
   store i32 %1, i32* %2, align 1
   %3 = extractvalue { i8, i32 } %ret, 0
   ret i8 %3
 }
 
 declare { i8, i64 } @llvm.x86.addcarry.u64(i8, i64, i64)
 
 define i8 @test_addcarry_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
-; NOADX-LABEL: test_addcarry_u64:
-; NOADX:       ## %bb.0:
-; NOADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; NOADX-NEXT:    adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
-; NOADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; NOADX-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; NOADX-NEXT:    retq ## encoding: [0xc3]
-;
-; ADX-LABEL: test_addcarry_u64:
-; ADX:       ## %bb.0:
-; ADX-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
-; ADX-NEXT:    adcxq %rdx, %rsi ## encoding: [0x66,0x48,0x0f,0x38,0xf6,0xf2]
-; ADX-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
-; ADX-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
-; ADX-NEXT:    retq ## encoding: [0xc3]
+; CHECK-LABEL: test_addcarry_u64:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
+; CHECK-NEXT:    adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
+; CHECK-NEXT:    setb %al ## encoding: [0x0f,0x92,0xc0]
+; CHECK-NEXT:    movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
+; CHECK-NEXT:    retq ## encoding: [0xc3]
   %ret = call { i8, i64 } @llvm.x86.addcarry.u64(i8 %c, i64 %a, i64 %b)
   %1 = extractvalue { i8, i64 } %ret, 1
   %2 = bitcast i8* %ptr to i64*
   store i64 %1, i64* %2, align 1
   %3 = extractvalue { i8, i64 } %ret, 0
   ret i8 %3
 }
 
; CHECK-NEXT:    retq ## encoding: [0xc3]
   %2 = bitcast i8* %ptr to i64*
   store i64 %1, i64* %2, align 1
   %3 = extractvalue { i8, i64 } %ret, 0
   ret i8 %3
 }
 
 ; Try a version with loads. Previously we crashed on this.
 define i32 @load_crash(i64* nocapture readonly %a, i64* nocapture readonly %b, i64* %res)  {
-; NOADX-LABEL: load_crash:
-; NOADX:       ## %bb.0:
-; NOADX-NEXT:    movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
-; NOADX-NEXT:    xorl %ecx, %ecx ## encoding: [0x31,0xc9]
-; NOADX-NEXT:    addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
-; NOADX-NEXT:    adcq (%rsi), %rax ## encoding: [0x48,0x13,0x06]
-; NOADX-NEXT:    setb %cl ## encoding: [0x0f,0x92,0xc1]
-; NOADX-NEXT:    movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
-; NOADX-NEXT:    movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
-; NOADX-NEXT:    retq ## encoding: [0xc3]
-;
-; ADX-LABEL: load_crash:
-; ADX:       ## %bb.0:
-; ADX-NEXT:    movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
-; ADX-NEXT:    xorl %ecx, %ecx ## encoding: [0x31,0xc9]
-; ADX-NEXT:    addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
-; ADX-NEXT:    adcxq (%rsi), %rax ## encoding: [0x66,0x48,0x0f,0x38,0xf6,0x06]
-; ADX-NEXT:    setb %cl ## encoding: [0x0f,0x92,0xc1]
-; ADX-NEXT:    movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
-; ADX-NEXT:    movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
-; ADX-NEXT:    retq ## encoding: [0xc3]
+; CHECK-LABEL: load_crash:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
+; CHECK-NEXT:    xorl %ecx, %ecx ## encoding: [0x31,0xc9]
+; CHECK-NEXT:    addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
+; CHECK-NEXT:    adcq (%rsi), %rax ## encoding: [0x48,0x13,0x06]
+; CHECK-NEXT:    setb %cl ## encoding: [0x0f,0x92,0xc1]
+; CHECK-NEXT:    movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
+; CHECK-NEXT:    movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
+; CHECK-NEXT:    retq ## encoding: [0xc3]
   %1 = load i64, i64* %a, align 8
   %2 = load i64, i64* %b, align 8
   %3 = bitcast i64* %res to i8*
   %4 = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 0, i64 %1, i64 %2)
   %5 = extractvalue { i8, i64 } %4, 1
   %6 = bitcast i8* %3 to i64*
   store i64 %5, i64* %6, align 1
   %7 = extractvalue { i8, i64 } %4, 0

llvm/trunk/test/CodeGen/X86/pr32282.ll

 ; X86-NEXT:    notl %eax
 ; X86-NEXT:    movl d+4, %ecx
 ; X86-NEXT:    notl %ecx
 ; X86-NEXT:    andl $701685459, %ecx # imm = 0x29D2DED3
 ; X86-NEXT:    andl $-564453154, %eax # imm = 0xDE5B20DE
 ; X86-NEXT:    shrdl $21, %ecx, %eax
 ; X86-NEXT:    shrl $21, %ecx
 ; X86-NEXT:    andl $-2, %eax
-; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:    addl $7, %eax
-; X86-NEXT:    adcxl %ecx, %edx
-; X86-NEXT:    pushl %edx
+; X86-NEXT:    adcl $0, %ecx
+; X86-NEXT:    pushl %ecx
 ; X86-NEXT:    .cfi_adjust_cfa_offset 4
 ; X86-NEXT:    pushl %eax
 ; X86-NEXT:    .cfi_adjust_cfa_offset 4
 ; X86-NEXT:    pushl $0
 ; X86-NEXT:    .cfi_adjust_cfa_offset 4
 ; X86-NEXT:    pushl $0
 ; X86-NEXT:    .cfi_adjust_cfa_offset 4
 ; X86-NEXT:    calll __divdi3

llvm/trunk/test/CodeGen/X86/pr32284.ll

 ; 686-O0-NEXT:    setne {{[0-9]+}}(%esp)
 ; 686-O0-NEXT:    movl var_5, %ecx
 ; 686-O0-NEXT:    movl %ecx, %edx
 ; 686-O0-NEXT:    sarl $31, %edx
 ; 686-O0-NEXT:    movl %ecx, %esi
 ; 686-O0-NEXT:    subl $-1, %esi
 ; 686-O0-NEXT:    sete %bl
 ; 686-O0-NEXT:    movzbl %bl, %edi
-; 686-O0-NEXT:    xorl %ebp, %ebp
 ; 686-O0-NEXT:    addl $7093, %ecx # imm = 0x1BB5
-; 686-O0-NEXT:    adcxl %ebp, %edx
+; 686-O0-NEXT:    adcl $0, %edx
 ; 686-O0-NEXT:    subl %edi, %ecx
 ; 686-O0-NEXT:    sbbl $0, %edx
 ; 686-O0-NEXT:    setl %bl
 ; 686-O0-NEXT:    movzbl %bl, %edi
 ; 686-O0-NEXT:    movl %edi, var_57
 ; 686-O0-NEXT:    movl $0, var_57+4
 ; 686-O0-NEXT:    movl var_5, %edi
 ; 686-O0-NEXT:    subl $-1, %edi
 ; 686-O0-NEXT:    sete %bl
 ; 686-O0-NEXT:    movzbl %bl, %ebp
 ; 686-O0-NEXT:    movl %ebp, _ZN8struct_210member_2_0E
 ; 686-O0-NEXT:    movl $0, _ZN8struct_210member_2_0E+4
 ; 686-O0-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; 686-O0-NEXT:    movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; 686-O0-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; 686-O0-NEXT:    movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; 686-O0-NEXT:    movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; 686-O0-NEXT:    movl %edi, (%esp) # 4-byte Spill
 ; 686-O0-NEXT:    addl $24, %esp
 ; 686-O0-NEXT:    .cfi_def_cfa_offset 20
 ; 686-O0-NEXT:    popl %esi
 ; 686-O0-NEXT:    .cfi_def_cfa_offset 16
 ; 686-O0-NEXT:    popl %edi
 ; 686-O0-NEXT:    .cfi_def_cfa_offset 12
 ; 686-O0-NEXT:    popl %ebx
 ; 686-O0-NEXT:    .cfi_def_cfa_offset 8
 ; 686-O0-NEXT:    popl %ebp
 ; 686-O0-NEXT:    .cfi_def_cfa_offset 4
 ; 686-O0-NEXT:    retl
 ;
 ; 686-LABEL: f1:
 ; 686:       # %bb.0: # %entry
-; 686-NEXT:    pushl %edi
-; 686-NEXT:    .cfi_def_cfa_offset 8
 ; 686-NEXT:    pushl %esi
-; 686-NEXT:    .cfi_def_cfa_offset 12
+; 686-NEXT:    .cfi_def_cfa_offset 8
 ; 686-NEXT:    subl $1, %esp
-; 686-NEXT:    .cfi_def_cfa_offset 13
-; 686-NEXT:    .cfi_offset %esi, -12
-; 686-NEXT:    .cfi_offset %edi, -8
+; 686-NEXT:    .cfi_def_cfa_offset 9
+; 686-NEXT:    .cfi_offset %esi, -8
 ; 686-NEXT:    movl var_5, %edx
 ; 686-NEXT:    movl %edx, %eax
 ; 686-NEXT:    xorl $208307499, %eax # imm = 0xC6A852B
 ; 686-NEXT:    movl %edx, %esi
 ; 686-NEXT:    sarl $31, %esi
 ; 686-NEXT:    movl %esi, %ecx
 ; 686-NEXT:    xorl $-2, %ecx
 ; 686-NEXT:    orl %eax, %ecx
 ; 686-NEXT:    setne (%esp)
 ; 686-NEXT:    movl %edx, %ecx
 ; 686-NEXT:    andl %esi, %ecx
 ; 686-NEXT:    xorl %eax, %eax
 ; 686-NEXT:    cmpl $-1, %ecx
 ; 686-NEXT:    sete %al
 ; 686-NEXT:    xorl %ecx, %ecx
 ; 686-NEXT:    cmpl $-1, %edx
 ; 686-NEXT:    sete %cl
-; 686-NEXT:    xorl %edi, %edi
 ; 686-NEXT:    addl $7093, %edx # imm = 0x1BB5
-; 686-NEXT:    adcxl %esi, %edi
+; 686-NEXT:    adcl $0, %esi
 ; 686-NEXT:    cmpl %ecx, %edx
-; 686-NEXT:    sbbl $0, %edi
+; 686-NEXT:    sbbl $0, %esi
 ; 686-NEXT:    setl %cl
 ; 686-NEXT:    movzbl %cl, %ecx
 ; 686-NEXT:    movl %ecx, var_57
 ; 686-NEXT:    movl $0, var_57+4
 ; 686-NEXT:    movl %eax, _ZN8struct_210member_2_0E
 ; 686-NEXT:    movl $0, _ZN8struct_210member_2_0E+4
 ; 686-NEXT:    addl $1, %esp
-; 686-NEXT:    .cfi_def_cfa_offset 12
-; 686-NEXT:    popl %esi
 ; 686-NEXT:    .cfi_def_cfa_offset 8
-; 686-NEXT:    popl %edi
+; 686-NEXT:    popl %esi
 ; 686-NEXT:    .cfi_def_cfa_offset 4
 ; 686-NEXT:    retl
 entry:
   %a = alloca i8, align 1
   %0 = load i32, i32* @var_5, align 4
   %conv = sext i32 %0 to i64
   %add = add nsw i64 %conv, 8381627093
   %tobool = icmp ne i64 %add, 0

llvm/trunk/test/CodeGen/X86/stack-folding-adx-x86_64.ll

-; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+adx < %s | FileCheck %s
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+adx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ADX
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=-adx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=NOADX
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-unknown"
 
 ; Stack reload folding tests.
 ;
 ; By including a nop call with sideeffects we can force a partial register spill of the
 ; relevant registers and check that the reload is correctly folded into the instruction.
 
 define i8 @stack_fold_addcarry_u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3) {
   ;CHECK-LABEL: stack_fold_addcarry_u32
-  ;CHECK:       adcxl {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 4-byte Folded Reload
+  ;CHECK:       adcl {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 4-byte Folded Reload
   %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
   %2 = tail call i8 @llvm.x86.addcarry.u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3)
   ret i8 %2;
 }
 declare i8 @llvm.x86.addcarry.u32(i8, i32, i32, i8*)
 
 define i8 @stack_fold_addcarry_u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3) {
   ;CHECK-LABEL: stack_fold_addcarry_u64
-  ;CHECK:       adcxq {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 8-byte Folded Reload
+  ;CHECK:       adcq {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 8-byte Folded Reload
   %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
   %2 = tail call i8 @llvm.x86.addcarry.u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3)
   ret i8 %2;
 }
 declare i8 @llvm.x86.addcarry.u64(i8, i64, i64, i8*)
 
 define i8 @stack_fold_addcarryx_u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3) {
   ;CHECK-LABEL: stack_fold_addcarryx_u32
-  ;CHECK:       adcxl {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 4-byte Folded Reload
+  ;CHECK:       adcl {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 4-byte Folded Reload
   %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
   %2 = tail call i8 @llvm.x86.addcarryx.u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3)
   ret i8 %2;
 }
 declare i8 @llvm.x86.addcarryx.u32(i8, i32, i32, i8*)
 
 define i8 @stack_fold_addcarryx_u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3) {
   ;CHECK-LABEL: stack_fold_addcarryx_u64
-  ;CHECK:       adcxq {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 8-byte Folded Reload
+  ;CHECK:       adcq {{-?[0-9]*}}(%rsp), %{{.*}} {{.*#+}} 8-byte Folded Reload
   %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
   %2 = tail call i8 @llvm.x86.addcarryx.u64(i8 %a0, i64 %a1, i64 %a2, i8* %a3)
   ret i8 %2;
 }
 declare i8 @llvm.x86.addcarryx.u64(i8, i64, i64, i8*)
 
 define i8 @stack_fold_subborrow_u32(i8 %a0, i32 %a1, i32 %a2, i8* %a3) {
   ;CHECK-LABEL: stack_fold_subborrow_u32