add IR flags to MI

[mcberg2017]

Summary

Initial support for nsw, nuw and exact flags in MI

[mcberg2017]

I have a test case which will show shortly...

[mcberg2017]

With the appropriate test file...

[spatel]

Are there MI transforms that would use these flags?
cc @nlopes - if we add these flags, then we also add the complexity of poison to this layer?

[mcberg2017]

The flags were requested for support in GlobalIsel, where there is a plan to make use of them once they are available. The path through SelectionDAG could also make use of the flags.

[nlopes]

Sure, adding nsw/nuw brings in poison. I didn't study all the MI transformations going on, so I can't comment on whether this is a big burden or not, but without such a study introducing poison is dangerous.
SDAG already has nsw/nuw IIRC, though. But I don't think there was a thorough study of the implications at the time either.

[mcberg2017]

All the nsw/nuw context is set above SDAG currently in code that is common to both GlobalIsel and SDAG, meaning adding them to MI should be analogous to SDAG as a pass through and for detection of already derived context for actions and side effects. Currently SDAG does have some DAG combining opts that utilize these flags. MI should too for GlobalIsel to map existing optimizations and functionality, else GlobalIsel will be handicapped. Having said that, if we do due diligence to map SDAG context in GlobalIsel, then there should be no new poison state, only that which currently exists. We should also keep the door open for new SDAG optimizations under nsw/nuw to map into that space to provide parity of support.

[spatel]

In D51738#1229266, @mcberg2017 wrote:

Having said that, if we do due diligence to map SDAG context in GlobalIsel, then there should be no new poison state, only that which currently exists.

Agree, but I don't think there has been any thorough study of the poison state in SDAG yet. But it's also true that we don't use those flags for very much, so there isn't much chance for disaster.

This patch is straightforward enough, so I won't impede it, but whoever is working on the translation to GlobalISel/MI transforms should be aware of the danger.

LGTM.

include/llvm/CodeGen/MachineInstr.h

enum MIFlag {
     FmNsz        = 1 << 6,              // Instruction is not required to retain
                                         // signed zero values.
     FmArcp       = 1 << 7,              // Instruction supports Fast math
                                         // reciprocal approximations.
     FmContract   = 1 << 8,              // Instruction supports Fast math
                                         // contraction operations like fma.
     FmAfn        = 1 << 9,              // Instruction may map to Fast math
                                         // instrinsic approximation.
-    FmReassoc    = 1 << 10              // Instruction supports Fast math
+    FmReassoc    = 1 << 10,             // Instruction supports Fast math
                                         // reassociation of operand order.
+    NoUWrap      = 1 << 11,             // Instruction supports binary operator
+                                        // no unsigned wrap.
+    NoSWrap      = 1 << 12,             // Instruction supports binary operator
+                                        // no signed wrap.
+    IsExact      = 1 << 13              // Instruction supports division is
+                                        // known to be exact.
   };
 
 private:
   const MCInstrDesc *MCID;              // Instruction descriptor.
   MachineBasicBlock *Parent = nullptr;  // Pointer to the owning basic block.
 
   // Operands are allocated by an ArrayRecycler.
   MachineOperand *Operands = nullptr;   // Pointer to the first operand.

lib/CodeGen/MIRParser/MILexer.h

enum TokenKind {
     kw_frame_destroy,
     kw_nnan,
     kw_ninf,
     kw_nsz,
     kw_arcp,
     kw_contract,
     kw_afn,
     kw_reassoc,
+    kw_nuw,
+    kw_nsw,
+    kw_exact,
     kw_debug_location,
     kw_cfi_same_value,
     kw_cfi_offset,
     kw_cfi_rel_offset,
     kw_cfi_def_cfa_register,
     kw_cfi_def_cfa_offset,
     kw_cfi_adjust_cfa_offset,
     kw_cfi_escape,

lib/CodeGen/MIRParser/MILexer.cpp

return StringSwitch<MIToken::TokenKind>(Identifier)
       .Case("frame-destroy", MIToken::kw_frame_destroy)
       .Case("nnan", MIToken::kw_nnan)
       .Case("ninf", MIToken::kw_ninf)
       .Case("nsz", MIToken::kw_nsz)
       .Case("arcp", MIToken::kw_arcp)
       .Case("contract", MIToken::kw_contract)
       .Case("afn", MIToken::kw_afn)
       .Case("reassoc", MIToken::kw_reassoc)
+      .Case("nuw" , MIToken::kw_nuw)
+      .Case("nsw" , MIToken::kw_nsw)
+      .Case("exact" , MIToken::kw_exact)
       .Case("debug-location", MIToken::kw_debug_location)
       .Case("same_value", MIToken::kw_cfi_same_value)
       .Case("offset", MIToken::kw_cfi_offset)
       .Case("rel_offset", MIToken::kw_cfi_rel_offset)
       .Case("def_cfa_register", MIToken::kw_cfi_def_cfa_register)
       .Case("def_cfa_offset", MIToken::kw_cfi_def_cfa_offset)
       .Case("adjust_cfa_offset", MIToken::kw_cfi_adjust_cfa_offset)
       .Case("escape", MIToken::kw_cfi_escape)

lib/CodeGen/MIRParser/MIParser.cpp

bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
   while (Token.is(MIToken::kw_frame_setup) ||
          Token.is(MIToken::kw_frame_destroy) ||
          Token.is(MIToken::kw_nnan) ||
          Token.is(MIToken::kw_ninf) ||
          Token.is(MIToken::kw_nsz) ||
          Token.is(MIToken::kw_arcp) ||
          Token.is(MIToken::kw_contract) ||
          Token.is(MIToken::kw_afn) ||
-         Token.is(MIToken::kw_reassoc)) {
+         Token.is(MIToken::kw_reassoc) ||
+         Token.is(MIToken::kw_nuw) ||
+         Token.is(MIToken::kw_nsw) ||
+         Token.is(MIToken::kw_exact)) {
     // Mine frame and fast math flags
     if (Token.is(MIToken::kw_frame_setup))
       Flags |= MachineInstr::FrameSetup;
     if (Token.is(MIToken::kw_frame_destroy))
       Flags |= MachineInstr::FrameDestroy;
     if (Token.is(MIToken::kw_nnan))
       Flags |= MachineInstr::FmNoNans;
     if (Token.is(MIToken::kw_ninf))
       Flags |= MachineInstr::FmNoInfs;
     if (Token.is(MIToken::kw_nsz))
       Flags |= MachineInstr::FmNsz;
     if (Token.is(MIToken::kw_arcp))
       Flags |= MachineInstr::FmArcp;
     if (Token.is(MIToken::kw_contract))
       Flags |= MachineInstr::FmContract;
     if (Token.is(MIToken::kw_afn))
       Flags |= MachineInstr::FmAfn;
     if (Token.is(MIToken::kw_reassoc))
       Flags |= MachineInstr::FmReassoc;
+    if (Token.is(MIToken::kw_nuw))
+      Flags |= MachineInstr::NoUWrap;
+    if (Token.is(MIToken::kw_nsw))
+      Flags |= MachineInstr::NoSWrap;
+    if (Token.is(MIToken::kw_exact))
+      Flags |= MachineInstr::IsExact;
 
     lex();
   }
   if (Token.isNot(MIToken::Identifier))
     return error("expected a machine instruction");
   StringRef InstrName = Token.stringValue();
   if (parseInstrName(InstrName, OpCode))
     return error(Twine("unknown machine instruction name '") + InstrName + "'");

lib/CodeGen/MIRPrinter.cpp

void MIPrinter::print(const MachineInstr &MI) {
   if (MI.getFlag(MachineInstr::FmArcp))
     OS << "arcp ";
   if (MI.getFlag(MachineInstr::FmContract))
     OS << "contract ";
   if (MI.getFlag(MachineInstr::FmAfn))
     OS << "afn ";
   if (MI.getFlag(MachineInstr::FmReassoc))
     OS << "reassoc ";
+  if (MI.getFlag(MachineInstr::NoUWrap))
+    OS << "nuw ";
+  if (MI.getFlag(MachineInstr::NoSWrap))
+    OS << "nsw ";
+  if (MI.getFlag(MachineInstr::IsExact))
+    OS << "exact ";
 
   OS << TII->getName(MI.getOpcode());
   if (I < E)
     OS << ' ';
 
   bool NeedComma = false;
   for (; I < E; ++I) {
     if (NeedComma)

lib/CodeGen/MachineInstr.cpp

void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
   if (getFlag(MachineInstr::FmArcp))
     OS << "arcp ";
   if (getFlag(MachineInstr::FmContract))
     OS << "contract ";
   if (getFlag(MachineInstr::FmAfn))
     OS << "afn ";
   if (getFlag(MachineInstr::FmReassoc))
     OS << "reassoc ";
+  if (getFlag(MachineInstr::NoUWrap))
+    OS << "nuw ";
+  if (getFlag(MachineInstr::NoSWrap))
+    OS << "nsw ";
+  if (getFlag(MachineInstr::IsExact))
+    OS << "exact ";
 
   // Print the opcode name.
   if (TII)
     OS << TII->getName(getOpcode());
   else
     OS << "UNKNOWN";
 
   if (SkipOpers)

test/CodeGen/MIR/X86/copyIRflags.mir

 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
 # This test ensures that the MIR parser parses the fast math instruction flags.
 
 ...
 ---
 name:            baz
 body: |
   bb.0.entry:
     liveins: $eax
   
-    $eax = ADD32rr $eax, killed $eax, implicit-def dead $eflags
-    ; CHECK:     $eax = ADD32rr $eax, killed $eax, implicit-def dead $eflags
-    $eax = ADD32rr $eax, killed $eax, implicit-def dead $eflags
-    ; CHECK:     $eax = SAR32ri $eax, 1, implicit-def dead $eflags
-    $eax = SAR32ri $eax, 1, implicit-def dead $eflags
+    $eax = nsw ADD32rr $eax, killed $eax, implicit-def dead $eflags
+    ; CHECK:     $eax = nuw ADD32rr $eax, killed $eax, implicit-def dead $eflags
+    $eax = nuw ADD32rr $eax, killed $eax, implicit-def dead $eflags
+    ; CHECK:     $eax = exact SAR32ri $eax, 1, implicit-def dead $eflags
+    $eax = exact SAR32ri $eax, 1, implicit-def dead $eflags
     ; CHECK:     RET 0, $eax
     RET 0, $eax
 
 ...