D50648 SystemZ tests updated

[jonpa]

Summary

Since I can't update the diff of D50648 directly, I here provide the SystemZ test updates.

[kparzysz]

I included the testcase changes into D50648, so this patch is no longer necessary.

lib/CodeGen/RegisterCoalescer.cpp

for (; BI != IntB.end() && ASeg.end >= BI->start; ++BI) {
         return true;
     }
   }
   return false;
 }
 
 /// Copy segments with value number @p SrcValNo from liverange @p Src to live
 /// range @Dst and use value number @p DstValNo there.
-static void addSegmentsWithValNo(LiveRange &Dst, VNInfo *DstValNo,
+static bool addSegmentsWithValNo(LiveRange &Dst, VNInfo *DstValNo,
                                  const LiveRange &Src, const VNInfo *SrcValNo) {
+  bool Added = false;
   for (const LiveRange::Segment &S : Src.segments) {
     if (S.valno != SrcValNo)
       continue;
+    Added = true;
     Dst.addSegment(LiveRange::Segment(S.start, S.end, DstValNo));
   }
+  return Added;
 }
 
 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
                                                  MachineInstr *CopyMI) {
   assert(!CP.isPhys());
 
   LiveInterval &IntA =
       LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
for (LiveInterval::SubRange &SA : IntA.subranges()) {
       assert(ASubValNo != nullptr);
 
       IntB.refineSubRanges(Allocator, SA.LaneMask,
           [&Allocator,&SA,CopyIdx,ASubValNo](LiveInterval::SubRange &SR) {
         VNInfo *BSubValNo = SR.empty()
           ? SR.getNextValue(CopyIdx, Allocator)
           : SR.getVNInfoAt(CopyIdx);
         assert(BSubValNo != nullptr);
-        addSegmentsWithValNo(SR, BSubValNo, SA, ASubValNo);
+        if (addSegmentsWithValNo(SR, BSubValNo, SA, ASubValNo))
+          BSubValNo->def = ASubValNo->def;
       });
     }
   }
 
   BValNo->def = AValNo->def;
   addSegmentsWithValNo(IntB, BValNo, IntA, AValNo);
   LLVM_DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
 

lib/CodeGen/VirtRegMap.cpp

for (MachineBasicBlock::instr_iterator
         unsigned PhysReg = VRM->getPhys(VirtReg);
         assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
                "Instruction uses unmapped VirtReg");
         assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
 
         // Preserve semantics of sub-register operands.
         unsigned SubReg = MO.getSubReg();
         if (SubReg != 0) {
-          if (NoSubRegLiveness) {
+          if (NoSubRegLiveness || !MRI->shouldTrackSubRegLiveness(VirtReg)) {
             // A virtual register kill refers to the whole register, so we may
             // have to add implicit killed operands for the super-register.  A
             // partial redef always kills and redefines the super-register.
             if ((MO.readsReg() && (MO.isDef() || MO.isKill())) ||
                 (MO.isDef() && subRegLiveThrough(*MI, PhysReg)))
               SuperKills.push_back(PhysReg);
 
             if (MO.isDef()) {

lib/Target/SystemZ/SystemZSubtarget.h

public:
   bool enableMachineScheduler() const override { return true; }
 
   // This is important for reducing register pressure in vector code.
   bool useAA() const override { return true; }
 
   // Always enable the early if-conversion pass.
   bool enableEarlyIfConversion() const override { return true; }
 
+  bool enableSubRegLiveness() const override { return true; }
+
   // Automatically generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
   // Return true if the target has the distinct-operands facility.
   bool hasDistinctOps() const { return HasDistinctOps; }
 
   // Return true if the target has the load/store-on-condition facility.
   bool hasLoadStoreOnCond() const { return HasLoadStoreOnCond; }

test/CodeGen/SystemZ/cmpxchg-06.ll

; CHECK: br %r14
   %val = extractvalue { i128, i1 } %pairval, 0
   ret i128 %val
 }
 
 ; Check generating the comparison result.
 ; CHECK-LABEL: f10
 ; CHECK-DAG: lg %r1, 8(%r3)
 ; CHECK-DAG: lg %r0, 0(%r3)
-; CHECK-DAG: lg %r13, 8(%r2)
-; CHECK-DAG: lg %r12, 0(%r2)
-; CHECK:     cdsg %r12, %r0, 0(%r4)
+; CHECK-DAG: lg {{%r[0-9]+}}, 8(%r2)
+; CHECK-DAG: lg [[REG:%r[0-9]+]], 0(%r2)
+; CHECK:     cdsg [[REG]], %r0, 0(%r4)
 ; CHECK-NEXT: ipm %r2
 ; CHECK-NEXT: afi %r2, -268435456
 ; CHECK-NEXT: srl %r2, 31
 ; CHECK: br %r14
 define i32 @f10(i128 %cmp, i128 %swap, i128 *%src) {
   %pairval = cmpxchg i128 *%src, i128 %cmp, i128 %swap seq_cst seq_cst
   %val = extractvalue { i128, i1 } %pairval, 1
   %res = zext i1 %val to i32
   ret i32 %res
 }
 
 declare void @g()
 
 ; Check using the comparison result for a branch.
 ; CHECK-LABEL: f11
-; CHECK-DAG: lg %r1, 8(%r3)
-; CHECK-DAG: lg %r0, 0(%r3)
-; CHECK-DAG: lg %r13, 8(%r2)
-; CHECK-DAG: lg %r12, 0(%r2)
-; CHECK:     cdsg %r12, %r0, 0(%r4)
-; CHECK-NEXT: jl [[LABEL:\.[^ ]*]]
-; CHECK: jg g
-; CHECK: [[LABEL]]:
-; CHECK: br %r14
+; CHECK-DAG:  lg %r1, 8(%r3)
+; CHECK-DAG:  lg %r0, 0(%r3)
+; CHECK-DAG:  lg %r3, 8(%r2)
+; CHECK-DAG:  lg %r2, 0(%r2)
+; CHECK:      cdsg %r2, %r0, 0(%r4)
+; CHECK-NEXT: jge g
+; CHECK:      br %r14
 define void @f11(i128 %cmp, i128 %swap, i128 *%src) {
   %pairval = cmpxchg i128 *%src, i128 %cmp, i128 %swap seq_cst seq_cst
   %cond = extractvalue { i128, i1 } %pairval, 1
   br i1 %cond, label %call, label %exit
 
 call:
   tail call void @g()
   br label %exit
 
 exit:
   ret void
 }
 
 ; ... and the same with the inverted direction.
 ; CHECK-LABEL: f12
-; CHECK-DAG: lg %r1, 8(%r3)
-; CHECK-DAG: lg %r0, 0(%r3)
-; CHECK-DAG: lg %r13, 8(%r2)
-; CHECK-DAG: lg %r12, 0(%r2)
-; CHECK:     cdsg %r12, %r0, 0(%r4)
-; CHECK-NEXT: jl [[LABEL:\.[^ ]*]]
-; CHECK: br %r14
-; CHECK: [[LABEL]]:
-; CHECK: jg g
+; CHECK-DAG:  lg %r1, 8(%r3)
+; CHECK-DAG:  lg %r0, 0(%r3)
+; CHECK-DAG:  lg %r3, 8(%r2)
+; CHECK-DAG:  lg %r2, 0(%r2)
+; CHECK:      cdsg %r2, %r0, 0(%r4)
+; CHECK-NEXT: jgl g
+; CHECK:      br %r14
 define void @f12(i128 %cmp, i128 %swap, i128 *%src) {
   %pairval = cmpxchg i128 *%src, i128 %cmp, i128 %swap seq_cst seq_cst
   %cond = extractvalue { i128, i1 } %pairval, 1
   br i1 %cond, label %exit, label %call
 
 call:
   tail call void @g()
   br label %exit
 
 exit:
   ret void
 }
 

test/CodeGen/SystemZ/int-ssub-06.ll

; CHECK: br %r14
   store i32 %val, i32 *%res
   ret i1 %obit
 }
 
 ; Check the next value up, which is treated as a negative value
 ; and must use a register.
 define zeroext i1 @f5(i32 %dummy, i32 %a, i32 *%res) {
 ; CHECK-LABEL: f5:
-; CHECK: llilh [[REG1:%r[0-5]]], 32768
+; CHECK: iilf [[REG1:%r[0-5]]], 2147483648
 ; CHECK: sr %r3, [[REG1]]
 ; CHECK-DAG: st %r3, 0(%r4)
 ; CHECK-DAG: ipm [[REG:%r[0-5]]]
 ; CHECK-DAG: afi [[REG]], 1342177280
 ; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
 ; CHECK: br %r14
   %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 2147483648)
   %val = extractvalue {i32, i1} %t, 0
; CHECK: br %r14
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32 *%res
   ret i1 %obit
 }
 
 ; Check the next value down, which must use a register.
 define zeroext i1 @f11(i32 %dummy, i32 %a, i32 *%res) {
 ; CHECK-LABEL: f11:
-; CHECK: llilh [[REG1:%r[0-5]]], 32768
+; CHECK: iilf [[REG1:%r[0-5]]], 2147483648
 ; CHECK: sr %r3, [[REG1]]
 ; CHECK-DAG: st %r3, 0(%r4)
 ; CHECK-DAG: ipm [[REG:%r[0-5]]]
 ; CHECK-DAG: afi [[REG]], 1342177280
 ; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
 ; CHECK: br %r14
   %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 -2147483648)
   %val = extractvalue {i32, i1} %t, 0