[7.0 branch] Update release notes (SystemZ, TableGen)

[uweigand]

Summary

This updates the 7.0 branch release notes to mention the SystemZ specific changes, and also the new support for multi-alternative patterns in TableGen (see D48545).

[hans]

looks great, thanks

(let me know if you'd like me to commit to the branch or if you'll do it yourself)

[uweigand]

I've checked it in now, thanks!

docs/ReleaseNotes.rst

  During this release ...
 
 
 Changes to the PowerPC Target
 -----------------------------
 
  During this release ...
 
+Changes to the SystemZ Target
+-----------------------------
+
+During this release the SystemZ target has:
+
+* Added support for vector registers in inline asm statements.
+
+* Added support for stackmaps, patchpoints, and the anyregcc
+  calling convention.
+
+* Changed the default function alignment to 16 bytes.
+
+* Improved codegen for condition code handling.
+
+* Improved instruction scheduling and microarchitecture tuning for z13/z14.
+
+* Fixed support for generating GCOV coverage data.
+
+* Fixed some codegen bugs.
+
 Changes to the X86 Target
 -------------------------
 
  During this release ...
 
 Changes to the AMDGPU Target
 -----------------------------
 

 ---------------------------------
 * ADDC/ADDE/SUBC/SUBE are now deprecated and will default to expand. Backends
   that wish to continue to use these opcodes should explicitely request so
   using ``setOperationAction`` in their ``TargetLowering``. New backends
   should use UADDO/ADDCARRY/USUBO/SUBCARRY instead of the deprecated opcodes.
 
 * The SETCCE opcode has now been removed in favor of SETCCCARRY.
 
+* TableGen now supports multi-alternative pattern fragments via the PatFrags
+  class.  PatFrag is now derived from PatFrags, which may require minor
+  changes to backends that directly access PatFrag members.
+
 External Open Source Projects Using LLVM 7
 ==========================================
 
 * A project...
 
 
 Additional Information
 ======================