[SystemZ] Use tablegen loops in SchedModels

[jonpa]

Summary

NFC changes to make TableGen files a bit more readable, by using loops instead of a lot of similar defs with just e.g. a latency value that changes.

[jonpa]

Thanks for helping me out with TableGen coding, Javed!

But you have LSU, LSU2, LSU3, ... . The first one would have to change to LSU1

I have sofar tried to avoid LSU1, FXa1, so I did

foreach Num = ["", "2", "3", "4", "5"]

, which seems to work. I would think this is ok, or? Only drawback here is that now there are in the subtarget files a separate definition for the "implicit 1\
" in some places. Not sure which is better...

Compared to trunk, there are in the tablegen file some extra variants, like FXa5 in z14 file, but that did not seem to matter - it seems that the produced cla\
ng binary is identical to that of trunk.

Any suggestions most welcome!

[javed.absar]

In D49598#1169672, @jonpa wrote:

Thanks for helping me out with TableGen coding, Javed!

But you have LSU, LSU2, LSU3, ... . The first one would have to change to LSU1

I have sofar tried to avoid LSU1, FXa1, so I did

foreach Num = ["", "2", "3", "4", "5"]

, which seems to work. I would think this is ok, or? Only drawback here is that now there are in the subtarget files a separate definition for the "implicit 1\
" in some places. Not sure which is better...

Compared to trunk, there are in the tablegen file some extra variants, like FXa5 in z14 file, but that did not seem to matter - it seems that the produced cla\
ng binary is identical to that of trunk.

Any suggestions most welcome!

Hi Jonas:

To avoid unnecessary defs (for dis-continous ranges), you can use range list like this:

foreach L = {1-3,6-8} in {
def "WLat"#L : SchedWrite;
}

I tried it out and it works.

[jonpa]

In D49598#1171580, @javed.absar wrote:

In D49598#1169672, @jonpa wrote:

Thanks for helping me out with TableGen coding, Javed!

But you have LSU, LSU2, LSU3, ... . The first one would have to change to LSU1

I have sofar tried to avoid LSU1, FXa1, so I did

foreach Num = ["", "2", "3", "4", "5"]

, which seems to work. I would think this is ok, or? Only drawback here is that now there are in the subtarget files a separate definition for the "implicit 1\
" in some places. Not sure which is better...

Compared to trunk, there are in the tablegen file some extra variants, like FXa5 in z14 file, but that did not seem to matter - it seems that the produced cla\
ng binary is identical to that of trunk.

Any suggestions most welcome!

Hi Jonas:

To avoid unnecessary defs (for dis-continous ranges), you can use range list like this:

foreach L = {1-3,6-8} in {
def "WLat"#L : SchedWrite;
}

I tried it out and it works.

Thanks, Javed. Still, it seemed that the clang binary was identically which should mean that any unused entries are simply ignored and left out from the generated tables. So perhaps using combined ranges per above is mostly cosmetical?

[javed.absar]

Yes Jonas it is purely cosmetic. Sometimes maybe be useful for code maintenance to show that certain records/values are not-possible

[uweigand]

I believe in this case it would be preferable to include the full range of latency values. We should try to keep the source as concise and straightforward as possible; if this results in some units being defined that aren't used, that doesn't seem to be a drawback to me. Also, for the common code parts, even if no current instruction uses any particular value, there may always be additional instructions in future processors.

[jonpa]

For some reason, the built clang binary (with the patch of a few days ago) makes some noise with diff now , but the binaries are of the exact same size, and SPEC output is identical...

Per off-line discussions I have now tried to simplify further the tablegen loops by including in some cases extra unused SchedWrites, e.g. VecBF3, etc. The binary size and SPEC output are still identical, so this looks fine.

We could make the loops even neater by using FXAa1, FXb1, etc... but then we also get a lot of FXa1 with the instructions, which I think is not quite as neat. Personally, I think it looks good as it is now without the FXa1...

[uweigand]

See inline comments. In general I agree with this approach.

lib/Target/SystemZ/SystemZSchedule.td

30

I believe you can omit the braces if there's just a single statement inside the foreach.

55

Why isn't this in the loop above as well?

58–59

I'd probably just but all of them in the loop too. Except the VecFPd, which is special.

[jonpa]

Thanks for review - patch updated per comments. Still NFC as before.

[jonpa]

In D49598#1174772, @jonpa wrote:

Thanks for review - patch updated per comments. Still NFC as before.

Tried to use clang-format a bit on this file.. Does it look ok, or should I change back? Thinking about the WLatLSU loop and the first/last spaces in the Num = [ "", .. "" ].

[uweigand]

A few more comments, LGTM with those changes.

lib/Target/SystemZ/SystemZScheduleZ13.td

64

Braces here as well.

85–86

For consistency with the general definition, you should move those (except VecFDd) up in the loop as well.

lib/Target/SystemZ/SystemZScheduleZ14.td

64

Same comment as for z13.

85–86

Same comment as for z13.

[uweigand]

Sorry, missed your last update.

I'm not sure clang-format understands .td files well. This case:

foreach L = 1 - 16 in def "WLat"#L#"LSU"
  : WriteSequence<[ !cast<SchedWrite>("WLat"#L), LSULatency ]>;

does indeed look a bit weird, I'd probably write something like:

foreach L = 1 - 16 in
  def "WLat"#L#"LSU" : WriteSequence<[ !cast<SchedWrite>("WLat"#L), LSULatency ]>;

[jonpa]

Updated per latest comments. NFC as before.

[uweigand]

LGTM, thanks.

[jonpa]

Thanks for review. Committed as r337909.

lib/Target/SystemZ/SystemZSchedule.td

 def GroupAlone : SchedWrite;
 def BeginGroup : SchedWrite;
 def EndGroup   : SchedWrite;
 
 // A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
 def LSULatency : SchedWrite;
 
 // Operand WriteLatencies.
-def WLat1 : SchedWrite;
-def WLat2 : SchedWrite;
-def WLat3 : SchedWrite;
-def WLat4 : SchedWrite;
-def WLat5 : SchedWrite;
-def WLat6 : SchedWrite;
-def WLat7 : SchedWrite;
-def WLat8 : SchedWrite;
-def WLat9 : SchedWrite;
-def WLat10 : SchedWrite;
-def WLat11 : SchedWrite;
-def WLat12 : SchedWrite;
-def WLat15 : SchedWrite;
-def WLat16 : SchedWrite;
-def WLat20 : SchedWrite;
-def WLat26 : SchedWrite;
-def WLat30 : SchedWrite;
-
-def WLat1LSU : WriteSequence<[WLat1, LSULatency]>;
-def WLat2LSU : WriteSequence<[WLat2, LSULatency]>;
-def WLat3LSU : WriteSequence<[WLat3, LSULatency]>;
-def WLat4LSU : WriteSequence<[WLat4, LSULatency]>;
-def WLat6LSU : WriteSequence<[WLat6, LSULatency]>;
-def WLat5LSU : WriteSequence<[WLat5, LSULatency]>;
-def WLat7LSU : WriteSequence<[WLat7, LSULatency]>;
-def WLat8LSU : WriteSequence<[WLat8, LSULatency]>;
-def WLat11LSU : WriteSequence<[WLat11, LSULatency]>;
-def WLat16LSU : WriteSequence<[WLat16, LSULatency]>;
+foreach L = 1 - 30 in def "WLat"#L : SchedWrite;
+
+foreach L = 1 - 16 in
+  def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
+                                      LSULatency]>;
 
 // ReadAdvances, used for the register operand next to a memory operand,
 // modelling that the register operand is needed later than the address
 // operands.
 def RegReadAdv : SchedRead;
 
+foreach Num = ["", "2", "3", "4", "5", "6"] in {
   // Fixed-point units
-def FXa         : SchedWrite;
-def FXa2        : SchedWrite;
-def FXa3        : SchedWrite;
-def FXa4        : SchedWrite;
-def FXb         : SchedWrite;
-def FXb2        : SchedWrite;
-def FXb3        : SchedWrite;
-def FXb4        : SchedWrite;
-def FXb5        : SchedWrite;
-def FXU         : SchedWrite;
-def FXU2        : SchedWrite;
-def FXU3        : SchedWrite;
-def FXU4        : SchedWrite;
-def FXU5        : SchedWrite;
-def FXU6        : SchedWrite;
-
+  def "FXa"#Num : SchedWrite;
+  def "FXb"#Num : SchedWrite;
+  def "FXU"#Num : SchedWrite;
   // Load/store unit
-def LSU         : SchedWrite;
-def LSU2        : SchedWrite;
-def LSU3        : SchedWrite;
-def LSU4        : SchedWrite;
-def LSU5        : SchedWrite;
-
+  def "LSU"#Num : SchedWrite;
+  // Vector sub units (z13 and later)
+  def "VecBF"#Num : SchedWrite;
+  def "VecDF"#Num : SchedWrite;
+  def "VecDFX"#Num : SchedWrite;
+  def "VecMul"#Num : SchedWrite;
+  def "VecStr"#Num : SchedWrite;
+  def "VecXsPm"#Num : SchedWrite;
   // Floating point unit (zEC12 and earlier)
-def FPU  : SchedWrite;
-def FPU2 : SchedWrite;
-def FPU4 : SchedWrite;
-def DFU  : SchedWrite;
-def DFU2 : SchedWrite;
-def DFU4 : SchedWrite;
+  def "FPU"#Num : SchedWrite;
+  def "DFU"#Num : SchedWrite;
+}
 
-// Vector sub units (z13 and later)
-def VecBF     : SchedWrite;
-def VecBF2    : SchedWrite;
-def VecBF4    : SchedWrite;
-def VecDF     : SchedWrite;
-def VecDF2    : SchedWrite;
-def VecDF4    : SchedWrite;
-def VecDFX    : SchedWrite;
-def VecDFX2   : SchedWrite;
-def VecDFX4   : SchedWrite;
-def VecFPd    : SchedWrite; // Blocking BFP div/sqrt unit.
-def VecMul    : SchedWrite;
-def VecStr    : SchedWrite;
-def VecXsPm   : SchedWrite;
-def VecXsPm2  : SchedWrite;
+def VecFPd : SchedWrite; // Blocking BFP div/sqrt unit.
 
-// Virtual branching unit
-def VBU       : SchedWrite;
+def VBU : SchedWrite; // Virtual branching unit
 
-// Millicode
-def MCD       : SchedWrite;
+def MCD : SchedWrite; // Millicode
 
 include "SystemZScheduleZ14.td"
 include "SystemZScheduleZ13.td"
 include "SystemZScheduleZEC12.td"
 include "SystemZScheduleZ196.td"
-

lib/Target/SystemZ/SystemZScheduleZ13.td

 def : ReadAdvance<RegReadAdv, 4>;
 
 // LoadLatency (above) is not used for instructions in this file. This is
 // instead the role of LSULatency, which is the latency value added to the
 // result of loads and instructions with folded memory operands.
 def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
 
 let NumMicroOps = 0 in {
-  def : WriteRes<WLat1, []> { let Latency = 1; }
-  def : WriteRes<WLat2, []> { let Latency = 2; }
-  def : WriteRes<WLat3, []> { let Latency = 3; }
-  def : WriteRes<WLat4, []> { let Latency = 4; }
-  def : WriteRes<WLat5, []> { let Latency = 5; }
-  def : WriteRes<WLat6, []> { let Latency = 6; }
-  def : WriteRes<WLat7, []> { let Latency = 7; }
-  def : WriteRes<WLat8, []> { let Latency = 8; }
-  def : WriteRes<WLat9, []> { let Latency = 9; }
-  def : WriteRes<WLat10, []> { let Latency = 10; }
-  def : WriteRes<WLat11, []> { let Latency = 11; }
-  def : WriteRes<WLat12, []> { let Latency = 12; }
-  def : WriteRes<WLat15, []> { let Latency = 15; }
-  def : WriteRes<WLat16, []> { let Latency = 16; }
-  def : WriteRes<WLat20, []> { let Latency = 20; }
-  def : WriteRes<WLat30, []> { let Latency = 30; }
+  foreach L = 1-30 in
+    def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
 }
 
 // Execution units.
 def Z13_FXaUnit     : ProcResource<2>;
 def Z13_FXbUnit     : ProcResource<2>;
 def Z13_LSUnit      : ProcResource<2>;
 def Z13_VecUnit     : ProcResource<2>;
 def Z13_VecFPdUnit  : ProcResource<2> { let BufferSize = 1; /* blocking */ }
 def Z13_VBUnit      : ProcResource<2>;
 def Z13_MCD         : ProcResource<1>;
 
 // Subtarget specific definitions of scheduling resources.
 let NumMicroOps = 0 in {
-  def : WriteRes<FXa,     [Z13_FXaUnit]>;
-  def : WriteRes<FXa2,    [Z13_FXaUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FXa3,    [Z13_FXaUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<FXa4,    [Z13_FXaUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<FXb,     [Z13_FXbUnit]>;
-  def : WriteRes<FXb2,    [Z13_FXbUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FXb3,    [Z13_FXbUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<FXb4,    [Z13_FXbUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<FXb5,    [Z13_FXbUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<LSU,     [Z13_LSUnit]>;
-  def : WriteRes<LSU2,    [Z13_LSUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<LSU3,    [Z13_LSUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<LSU4,    [Z13_LSUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<LSU5,    [Z13_LSUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<VecBF,   [Z13_VecUnit]>;
-  def : WriteRes<VecBF2,  [Z13_VecUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<VecBF4,  [Z13_VecUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<VecDF,   [Z13_VecUnit]>;
-  def : WriteRes<VecDF2,  [Z13_VecUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<VecDF4,  [Z13_VecUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<VecDFX,  [Z13_VecUnit]>;
-  def : WriteRes<VecDFX2, [Z13_VecUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<VecDFX4, [Z13_VecUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<VecFPd,  [Z13_VecFPdUnit]> { let ResourceCycles = [30]; }
+  def : WriteRes<FXa, [Z13_FXaUnit]>;
+  def : WriteRes<FXb, [Z13_FXbUnit]>;
+  def : WriteRes<LSU, [Z13_LSUnit]>;
+  def : WriteRes<VecBF,  [Z13_VecUnit]>;
+  def : WriteRes<VecDF,  [Z13_VecUnit]>;
+  def : WriteRes<VecDFX, [Z13_VecUnit]>;
   def : WriteRes<VecMul,  [Z13_VecUnit]>;
   def : WriteRes<VecStr,  [Z13_VecUnit]>;
   def : WriteRes<VecXsPm, [Z13_VecUnit]>;
-  def : WriteRes<VecXsPm2,[Z13_VecUnit]> { let ResourceCycles = [2]; }
-  // Virtual Branching Unit
-  def : WriteRes<VBU,     [Z13_VBUnit]>;
+  foreach Num = 2-5 in { let ResourceCycles = [Num] in {
+    def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z13_FXaUnit]>;
+    def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z13_FXbUnit]>;
+    def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z13_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z13_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z13_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z13_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z13_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z13_VecUnit]>;
+  }}
+
+  def : WriteRes<VecFPd,  [Z13_VecFPdUnit]> { let ResourceCycles = [30]; }
+
+  def : WriteRes<VBU,     [Z13_VBUnit]>; // Virtual Branching Unit
 }
 
 def : WriteRes<MCD, [Z13_MCD]> { let NumMicroOps = 3;
                                  let BeginGroup  = 1;
                                  let EndGroup    = 1; }
 
 // -------------------------- INSTRUCTIONS ---------------------------------- //
 

lib/Target/SystemZ/SystemZScheduleZ14.td

 def : ReadAdvance<RegReadAdv, 4>;
 
 // LoadLatency (above) is not used for instructions in this file. This is
 // instead the role of LSULatency, which is the latency value added to the
 // result of loads and instructions with folded memory operands.
 def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
 
 let NumMicroOps = 0 in {
-  def : WriteRes<WLat1, []> { let Latency = 1; }
-  def : WriteRes<WLat2, []> { let Latency = 2; }
-  def : WriteRes<WLat3, []> { let Latency = 3; }
-  def : WriteRes<WLat4, []> { let Latency = 4; }
-  def : WriteRes<WLat5, []> { let Latency = 5; }
-  def : WriteRes<WLat6, []> { let Latency = 6; }
-  def : WriteRes<WLat7, []> { let Latency = 7; }
-  def : WriteRes<WLat8, []> { let Latency = 8; }
-  def : WriteRes<WLat9, []> { let Latency = 9; }
-  def : WriteRes<WLat10, []> { let Latency = 10; }
-  def : WriteRes<WLat11, []> { let Latency = 11; }
-  def : WriteRes<WLat12, []> { let Latency = 12; }
-  def : WriteRes<WLat15, []> { let Latency = 15; }
-  def : WriteRes<WLat16, []> { let Latency = 16; }
-  def : WriteRes<WLat20, []> { let Latency = 20; }
-  def : WriteRes<WLat30, []> { let Latency = 30; }
+  foreach L = 1-30 in
+    def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
 }
 
 // Execution units.
 def Z14_FXaUnit     : ProcResource<2>;
 def Z14_FXbUnit     : ProcResource<2>;
 def Z14_LSUnit      : ProcResource<2>;
 def Z14_VecUnit     : ProcResource<2>;
 def Z14_VecFPdUnit  : ProcResource<2> { let BufferSize = 1; /* blocking */ }
 def Z14_VBUnit      : ProcResource<2>;
 def Z14_MCD         : ProcResource<1>;
 
 // Subtarget specific definitions of scheduling resources.
 let NumMicroOps = 0 in {
-  def : WriteRes<FXa,     [Z14_FXaUnit]>;
-  def : WriteRes<FXa2,    [Z14_FXaUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FXa3,    [Z14_FXaUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<FXa4,    [Z14_FXaUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<FXb,     [Z14_FXbUnit]>;
-  def : WriteRes<FXb2,    [Z14_FXbUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FXb3,    [Z14_FXbUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<FXb4,    [Z14_FXbUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<FXb5,    [Z14_FXbUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<LSU,     [Z14_LSUnit]>;
-  def : WriteRes<LSU2,    [Z14_LSUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<LSU3,    [Z14_LSUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<LSU4,    [Z14_LSUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<LSU5,    [Z14_LSUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<VecBF,   [Z14_VecUnit]>;
-  def : WriteRes<VecBF2,  [Z14_VecUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<VecBF4,  [Z14_VecUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<VecDF,   [Z14_VecUnit]>;
-  def : WriteRes<VecDF2,  [Z14_VecUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<VecDF4,  [Z14_VecUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<VecDFX,  [Z14_VecUnit]>;
-  def : WriteRes<VecDFX2, [Z14_VecUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<VecDFX4, [Z14_VecUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<VecFPd,  [Z14_VecFPdUnit]> { let ResourceCycles = [30]; }
+  def : WriteRes<FXa, [Z14_FXaUnit]>;
+  def : WriteRes<FXb, [Z14_FXbUnit]>;
+  def : WriteRes<LSU, [Z14_LSUnit]>;
+  def : WriteRes<VecBF,  [Z14_VecUnit]>;
+  def : WriteRes<VecDF,  [Z14_VecUnit]>;
+  def : WriteRes<VecDFX, [Z14_VecUnit]>;
   def : WriteRes<VecMul,  [Z14_VecUnit]>;
   def : WriteRes<VecStr,  [Z14_VecUnit]>;
   def : WriteRes<VecXsPm, [Z14_VecUnit]>;
-  def : WriteRes<VecXsPm2,[Z14_VecUnit]> { let ResourceCycles = [2]; }
-  // Virtual Branching Unit
-  def : WriteRes<VBU,     [Z14_VBUnit]>;
+  foreach Num = 2-5 in { let ResourceCycles = [Num] in {
+    def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z14_FXaUnit]>;
+    def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z14_FXbUnit]>;
+    def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z14_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z14_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z14_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z14_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z14_VecUnit]>;
+    def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z14_VecUnit]>;
+  }}
+
+  def : WriteRes<VecFPd,  [Z14_VecFPdUnit]> { let ResourceCycles = [30]; }
+
+  def : WriteRes<VBU,     [Z14_VBUnit]>; // Virtual Branching Unit
 }
 
 def : WriteRes<MCD, [Z14_MCD]> { let NumMicroOps = 3;
                                  let BeginGroup  = 1;
                                  let EndGroup    = 1; }
 
 // -------------------------- INSTRUCTIONS ---------------------------------- //
 

lib/Target/SystemZ/SystemZScheduleZ196.td

 def : ReadAdvance<RegReadAdv, 4>;
 
 // LoadLatency (above) is not used for instructions in this file. This is
 // instead the role of LSULatency, which is the latency value added to the
 // result of loads and instructions with folded memory operands.
 def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
 
 let NumMicroOps = 0 in {
-  def : WriteRes<WLat1, []> { let Latency = 1; }
-  def : WriteRes<WLat2, []> { let Latency = 2; }
-  def : WriteRes<WLat3, []> { let Latency = 3; }
-  def : WriteRes<WLat4, []> { let Latency = 4; }
-  def : WriteRes<WLat5, []> { let Latency = 5; }
-  def : WriteRes<WLat6, []> { let Latency = 6; }
-  def : WriteRes<WLat7, []> { let Latency = 7; }
-  def : WriteRes<WLat8, []> { let Latency = 8; }
-  def : WriteRes<WLat9, []> { let Latency = 9; }
-  def : WriteRes<WLat10, []> { let Latency = 10; }
-  def : WriteRes<WLat11, []> { let Latency = 11; }
-  def : WriteRes<WLat12, []> { let Latency = 12; }
-  def : WriteRes<WLat15, []> { let Latency = 15; }
-  def : WriteRes<WLat16, []> { let Latency = 16; }
-  def : WriteRes<WLat20, []> { let Latency = 20; }
-  def : WriteRes<WLat30, []> { let Latency = 30; }
+  foreach L = 1-30 in {
+    def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
+  }
 }
 
 // Execution units.
 def Z196_FXUnit : ProcResource<2>;
 def Z196_LSUnit : ProcResource<2>;
 def Z196_FPUnit : ProcResource<1>;
 def Z196_DFUnit : ProcResource<1>;
 def Z196_MCD    : ProcResource<1>;
 
 // Subtarget specific definitions of scheduling resources.
 let NumMicroOps = 0 in {
-  def : WriteRes<FXU,       [Z196_FXUnit]>;
-  def : WriteRes<FXU2,      [Z196_FXUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FXU3,      [Z196_FXUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<FXU4,      [Z196_FXUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<FXU5,      [Z196_FXUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<FXU6,      [Z196_FXUnit]> { let ResourceCycles = [6]; }
-  def : WriteRes<LSU,       [Z196_LSUnit]>;
-  def : WriteRes<LSU2,      [Z196_LSUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<LSU3,      [Z196_LSUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<LSU5,      [Z196_LSUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<FPU,       [Z196_FPUnit]>;
-  def : WriteRes<FPU2,      [Z196_FPUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FPU4,      [Z196_FPUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<DFU,       [Z196_DFUnit]>;
-  def : WriteRes<DFU2,      [Z196_DFUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<DFU4,      [Z196_DFUnit]> { let ResourceCycles = [4]; }
+  def : WriteRes<FXU, [Z196_FXUnit]>;
+  def : WriteRes<LSU, [Z196_LSUnit]>;
+  def : WriteRes<FPU, [Z196_FPUnit]>;
+  def : WriteRes<DFU, [Z196_DFUnit]>;
+  foreach Num = 2-6 in { let ResourceCycles = [Num] in {
+    def : WriteRes<!cast<SchedWrite>("FXU"#Num), [Z196_FXUnit]>;
+    def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
+    def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
+    def : WriteRes<!cast<SchedWrite>("DFU"#Num), [Z196_DFUnit]>;
+  }}
 }
 
 def : WriteRes<MCD, [Z196_MCD]> { let NumMicroOps = 3;
                                   let BeginGroup  = 1;
                                   let EndGroup    = 1; }
 
 // -------------------------- INSTRUCTIONS ---------------------------------- //
 

lib/Target/SystemZ/SystemZScheduleZEC12.td

 def : ReadAdvance<RegReadAdv, 4>;
 
 // LoadLatency (above) is not used for instructions in this file. This is
 // instead the role of LSULatency, which is the latency value added to the
 // result of loads and instructions with folded memory operands.
 def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
 
 let NumMicroOps = 0 in {
-  def : WriteRes<WLat1, []> { let Latency = 1; }
-  def : WriteRes<WLat2, []> { let Latency = 2; }
-  def : WriteRes<WLat3, []> { let Latency = 3; }
-  def : WriteRes<WLat4, []> { let Latency = 4; }
-  def : WriteRes<WLat5, []> { let Latency = 5; }
-  def : WriteRes<WLat6, []> { let Latency = 6; }
-  def : WriteRes<WLat7, []> { let Latency = 7; }
-  def : WriteRes<WLat8, []> { let Latency = 8; }
-  def : WriteRes<WLat9, []> { let Latency = 9; }
-  def : WriteRes<WLat10, []> { let Latency = 10; }
-  def : WriteRes<WLat11, []> { let Latency = 11; }
-  def : WriteRes<WLat12, []> { let Latency = 12; }
-  def : WriteRes<WLat15, []> { let Latency = 15; }
-  def : WriteRes<WLat16, []> { let Latency = 16; }
-  def : WriteRes<WLat20, []> { let Latency = 20; }
-  def : WriteRes<WLat30, []> { let Latency = 30; }
+  foreach L = 1-30 in {
+    def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
+  }
 }
 
 // Execution units.
 def ZEC12_FXUnit : ProcResource<2>;
 def ZEC12_LSUnit : ProcResource<2>;
 def ZEC12_FPUnit : ProcResource<1>;
 def ZEC12_DFUnit : ProcResource<1>;
 def ZEC12_VBUnit : ProcResource<1>;
 def ZEC12_MCD    : ProcResource<1>;
 
 // Subtarget specific definitions of scheduling resources.
 let NumMicroOps = 0 in {
-  def : WriteRes<FXU,  [ZEC12_FXUnit]>;
-  def : WriteRes<FXU2, [ZEC12_FXUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FXU3, [ZEC12_FXUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<FXU4, [ZEC12_FXUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<FXU5, [ZEC12_FXUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<FXU6, [ZEC12_FXUnit]> { let ResourceCycles = [6]; }
-  def : WriteRes<LSU,  [ZEC12_LSUnit]>;
-  def : WriteRes<LSU2, [ZEC12_LSUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<LSU3, [ZEC12_LSUnit]> { let ResourceCycles = [3]; }
-  def : WriteRes<LSU4, [ZEC12_LSUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<LSU5, [ZEC12_LSUnit]> { let ResourceCycles = [5]; }
-  def : WriteRes<FPU,  [ZEC12_FPUnit]>;
-  def : WriteRes<FPU2, [ZEC12_FPUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<FPU4, [ZEC12_FPUnit]> { let ResourceCycles = [4]; }
-  def : WriteRes<DFU,  [ZEC12_DFUnit]>;
-  def : WriteRes<DFU2, [ZEC12_DFUnit]> { let ResourceCycles = [2]; }
-  def : WriteRes<DFU4, [ZEC12_DFUnit]> { let ResourceCycles = [4]; }
+  def : WriteRes<FXU, [ZEC12_FXUnit]>;
+  def : WriteRes<LSU, [ZEC12_LSUnit]>;
+  def : WriteRes<FPU, [ZEC12_FPUnit]>;
+  def : WriteRes<DFU, [ZEC12_DFUnit]>;
+  foreach Num = 2-6 in { let ResourceCycles = [Num] in {
+    def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
+    def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
+    def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
+    def : WriteRes<!cast<SchedWrite>("DFU"#Num), [ZEC12_DFUnit]>;
+  }}
+
   def : WriteRes<VBU,  [ZEC12_VBUnit]>; // Virtual Branching Unit
 }
 
 def : WriteRes<MCD, [ZEC12_MCD]> { let NumMicroOps = 3;
                                    let BeginGroup  = 1;
                                    let EndGroup    = 1; }
 
 // -------------------------- INSTRUCTIONS ---------------------------------- //