[mips] Add assembler support for .set mips0 directive.

[tomatabacu]

Summary

This directive is used to reset the assembler options to their initial values.
Assembly programmers use it in conjunction with the ".set mipsX" directives.

This patch depends on the .set push/pop directive (http://reviews.llvm.org/D4821).

Contains work done by Matheus Almeida.

[tomatabacu]

Improved test.

[dsanders]

This patch will need updating after you remove the static variable from D4821.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

82–84

I don't think these 3 are supposed to be reset by '.set mips0'

[tomatabacu]

Updated to match the changes in D4821.
Rebased.
Addressed reviewer's concern.

[dsanders]

LGTM with a bug fix.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2742

Don't you need something like this?

AssemblerOptions.back()->setCurrentFeatures(AssemblerOptions.front()->getFeatures());

or this?

AssemblerOptions.back()->setFeatures(getAvailableFeatures());

The test case I have in mind is:

.set msa
addvi.w $w0, $w0, $w0
.set mips0
addvi.w $w0, $w0, $w0 ; Should be an invalid instruction
.set push
addvi.w $w0, $w0, $w0 ; Should be an invalid instruction
.set dsp
addvi.w $w0, $w0, $w0 ; Should be an invalid instruction
.set pop
addvi.w $w0, $w0, $w0 ; Should be an invalid instruction

I think the '.set pop' will accidentally re-enable MSA because the MipsAssemblerOptions object on the stack still has MSA enabled after the '.set mips0'.

[tomatabacu]

Fixed the bug.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

static const uint64_t AllArchRelatedMask =
       Mips::FeatureMips3_32 | Mips::FeatureMips3_32r2 | Mips::FeatureMips4 |
       Mips::FeatureMips4_32 | Mips::FeatureMips4_32r2 | Mips::FeatureMips5 |
       Mips::FeatureMips5_32r2 | Mips::FeatureMips32 | Mips::FeatureMips32r2 |
       Mips::FeatureMips32r6 | Mips::FeatureMips64 | Mips::FeatureMips64r2 |
       Mips::FeatureMips64r6 | Mips::FeatureCnMips | Mips::FeatureFP64Bit |
       Mips::FeatureGP64Bit | Mips::FeatureNaN2008;
 
 private:
   unsigned ATReg;
   bool Reorder;
   bool Macro;
   uint64_t Features;
 };
 }
 
 namespace {
 class MipsAsmParser : public MCTargetAsmParser {
   MipsTargetStreamer &getTargetStreamer() {
     MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
#include "MipsGenAsmMatcher.inc"
   bool reportParseError(SMLoc Loc, Twine ErrorMsg);
 
   bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
   bool parseRelocOperand(const MCExpr *&Res);
 
   const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
 
   bool isEvaluated(const MCExpr *Expr);
+  bool parseSetMips0Directive();
   bool parseSetArchDirective();
   bool parseSetFeature(uint64_t Feature);
   bool parseDirectiveCPLoad(SMLoc Loc);
   bool parseDirectiveCPSetup();
   bool parseDirectiveNaN();
   bool parseDirectiveSet();
   bool parseDirectiveOption();
 
bool MipsAsmParser::parseSetAssignment() {
   if (Sym)
     return reportParseError("symbol already defined");
   Sym = getContext().GetOrCreateSymbol(Name);
   Sym->setVariableValue(Value);
 
   return false;
 }
 
+bool MipsAsmParser::parseSetMips0Directive() {
+  Parser.Lex();
+  if (getLexer().isNot(AsmToken::EndOfStatement))
+    return reportParseError("unexpected token, expected end of statement");
+
+  // Reset assembler options to their initial values.
+  setAvailableFeatures(AssemblerOptions.front()->getFeatures());
+
+  getTargetStreamer().emitDirectiveSetMips0();
+  return false;
+}
+
 bool MipsAsmParser::parseSetArchDirective() {
   Parser.Lex();
   if (getLexer().isNot(AsmToken::Equal))
     return reportParseError("unexpected token, expected equals sign");
 
   Parser.Lex();
   StringRef Arch;
   if (Parser.parseIdentifier(Arch))
bool MipsAsmParser::parseDirectiveSet() {
   } else if (Tok.getString() == "nomips16") {
     return parseSetNoMips16Directive();
   } else if (Tok.getString() == "nomicromips") {
     getTargetStreamer().emitDirectiveSetNoMicroMips();
     Parser.eatToEndOfStatement();
     return false;
   } else if (Tok.getString() == "micromips") {
     return parseSetFeature(Mips::FeatureMicroMips);
+  } else if (Tok.getString() == "mips0") {
+    return parseSetMips0Directive();
   } else if (Tok.getString() == "mips1") {
     return parseSetFeature(Mips::FeatureMips1);
   } else if (Tok.getString() == "mips2") {
     return parseSetFeature(Mips::FeatureMips2);
   } else if (Tok.getString() == "mips3") {
     return parseSetFeature(Mips::FeatureMips3);
   } else if (Tok.getString() == "mips4") {
     return parseSetFeature(Mips::FeatureMips4);

lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
                                    unsigned ReturnReg) {}
 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
 }
 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
   forbidModuleDirective();
 }
+void MipsTargetStreamer::emitDirectiveSetMips0() {}
 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
OS << "\t.frame\t$"
      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
 }
 
 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
   OS << "\t.set arch=" << Arch << "\n";
   MipsTargetStreamer::emitDirectiveSetArch(Arch);
 }
 
+void MipsTargetAsmStreamer::emitDirectiveSetMips0() { OS << "\t.set\tmips0\n"; }
+
 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
   OS << "\t.set\tmips1\n";
   MipsTargetStreamer::emitDirectiveSetMips1();
 }
 
 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
   OS << "\t.set\tmips2\n";
   MipsTargetStreamer::emitDirectiveSetMips2();

lib/Target/Mips/MipsTargetStreamer.h

public:
   virtual void emitDirectiveOptionPic0();
   virtual void emitDirectiveOptionPic2();
   virtual void emitFrame(unsigned StackReg, unsigned StackSize,
                          unsigned ReturnReg);
   virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff);
   virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff);
 
   virtual void emitDirectiveSetArch(StringRef Arch);
+  virtual void emitDirectiveSetMips0();
   virtual void emitDirectiveSetMips1();
   virtual void emitDirectiveSetMips2();
   virtual void emitDirectiveSetMips3();
   virtual void emitDirectiveSetMips4();
   virtual void emitDirectiveSetMips5();
   virtual void emitDirectiveSetMips32();
   virtual void emitDirectiveSetMips32R2();
   virtual void emitDirectiveSetMips32R6();
public:
   void emitDirectiveOptionPic0() override;
   void emitDirectiveOptionPic2() override;
   void emitFrame(unsigned StackReg, unsigned StackSize,
                  unsigned ReturnReg) override;
   void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
   void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
 
   void emitDirectiveSetArch(StringRef Arch) override;
+  void emitDirectiveSetMips0() override;
   void emitDirectiveSetMips1() override;
   void emitDirectiveSetMips2() override;
   void emitDirectiveSetMips3() override;
   void emitDirectiveSetMips4() override;
   void emitDirectiveSetMips5() override;
   void emitDirectiveSetMips32() override;
   void emitDirectiveSetMips32R2() override;
   void emitDirectiveSetMips32R6() override;

test/MC/Mips/set-mips0-directive.s

+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 | \
+# RUN:   FileCheck %s
+
+    .text
+    rotr  $7, $7, 22
+
+    .set mips32r6
+    mod   $2, $4, $6
+    .set mips0
+    rotr  $2, $2, 15
+
+    .set mips3
+    dadd  $4, $4, $4
+    .set mips0
+    rotr  $3, $3, 19
+
+# CHECK: rotr  $7, $7, 22
+
+# CHECK: .set mips32r6
+# CHECK: mod   $2, $4, $6
+# CHECK: .set mips0
+# CHECK: rotr  $2, $2, 15
+
+# CHECK: .set mips3
+# CHECK: dadd  $4, $4, $4
+# CHECK: .set mips0
+# CHECK: rotr  $3, $3, 19