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Differential D49283

[InstCombine] fold icmp pred (sub 0, X) C for vector type
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Authored by shchenz on Jul 13 2018, 1:34 AM.

Details

Reviewers
spatel
nemanjai
Commits
rGb972273f9849: [InstCombine] fold icmp pred (sub 0, X) C for vector type
rL337141: [InstCombine] fold icmp pred (sub 0, X) C for vector type
Summary

This is from D49238 code review comments.

Currently opt can fold scalar type for instruction pattern:

define i32 @Op1Negated_Scalar(i32 %x) {
  %sub = sub nsw i32 0, %x
  %cmp = icmp sgt i32 %sub, -1
  %cond = select i1 %cmp, i32 %sub, i32 %x
  ret i32 %cond
}

to

define i32 @Op1Negated_Scalar(i32 %x) {
  %sub = sub nsw i32 0, %x
  %cmp = icmp slt i32 %x, 0
  %cond = select i1 %cmp, i32 %sub, i32 %x
  ret i32 %cond
}

But it can not fold vector type for the same instruction pattern:

define <2 x i32> @Op1Negated_Vec(<2 x i32> %x) {
  %sub = sub nsw <2 x i32> zeroinitializer, %x
  %cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
  %cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x
  ret <2 x i32> %cond
}

We should also fold %cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1> to %cmp = icmp slt <2 x i32> %x, zeroinitializer as what we do for scalar type.

Note: there must be two uses of %sub in case Op1Negated_Vec(), %cmp and %cond, otherwise if only one use %cmp, icmp is folded in earlier function in visitICmpInst() -> foldICmpWithConstant() -> foldICmpSubConstant().

Diff Detail

Repository
rL LLVM

Event Timeline

shchenz created this revision.Jul 13 2018, 1:34 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptJul 13 2018, 1:34 AM
shchenz mentioned this in D49238: [InstCombine] add more SPFofSPF folding.Jul 13 2018, 1:38 AM
spatel accepted this revision.Jul 13 2018, 5:15 AM

Thanks for finding that! LGTM.

This revision is now accepted and ready to land.Jul 13 2018, 5:15 AM
Closed by commit rL337141: [InstCombine] fold icmp pred (sub 0, X) C for vector type (authored by shchenz). · Explain WhyJul 15 2018, 5:56 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Transforms/
InstCombine/
4 lines
test/
Transforms/
InstCombine/
35 lines
13 lines

Diff 155603

llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp

Show First 20 Lines • Show All 3,148 Lines • ▼ Show 20 Lines if (A && C && A == C && NoOp0WrapProblem && NoOp1WrapProblem &&
// Try not to increase register pressure. // Try not to increase register pressure.
BO0->hasOneUse() && BO1->hasOneUse()) BO0->hasOneUse() && BO1->hasOneUse())
return new ICmpInst(Pred, D, B); return new ICmpInst(Pred, D, B);
// icmp (0-X) < cst --> x > -cst // icmp (0-X) < cst --> x > -cst
if (NoOp0WrapProblem && ICmpInst::isSigned(Pred)) { if (NoOp0WrapProblem && ICmpInst::isSigned(Pred)) {
Value *X; Value *X;
if (match(BO0, m_Neg(m_Value(X)))) if (match(BO0, m_Neg(m_Value(X))))
if (ConstantInt *RHSC = dyn_cast<ConstantInt>(Op1)) if (Constant *RHSC = dyn_cast<Constant>(Op1))
if (!RHSC->isMinValue(/*isSigned=*/true)) if (RHSC->isNotMinSignedValue())
return new ICmpInst(I.getSwappedPredicate(), X, return new ICmpInst(I.getSwappedPredicate(), X,
ConstantExpr::getNeg(RHSC)); ConstantExpr::getNeg(RHSC));
} }
BinaryOperator *SRem = nullptr; BinaryOperator *SRem = nullptr;
// icmp (srem X, Y), Y // icmp (srem X, Y), Y
if (BO0 && BO0->getOpcode() == Instruction::SRem && Op1 == BO0->getOperand(1)) if (BO0 && BO0->getOpcode() == Instruction::SRem && Op1 == BO0->getOperand(1))
SRem = BO0; SRem = BO0;
▲ Show 20 Lines • Show All 2,061 Lines • Show Last 20 Lines

llvm/trunk/test/Transforms/InstCombine/abs_abs.ll

Show First 20 Lines • Show All 326 Lines • ▼ Show 20 Lines;
%cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
ret i32 %cond18 ret i32 %cond18
} }
; abs(abs(-x)) -> abs(-x) ; abs(abs(-x)) -> abs(-x)
define <2 x i32> @abs_abs_x02_vec(<2 x i32> %x) { define <2 x i32> @abs_abs_x02_vec(<2 x i32> %x) {
; CHECK-LABEL: @abs_abs_x02_vec( ; CHECK-LABEL: @abs_abs_x02_vec(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]] ; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[SUB]], <i32 -1, i32 -1> ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> [[X]] ; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> [[X]]
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt <2 x i32> [[COND]], zeroinitializer ; CHECK-NEXT: ret <2 x i32> [[COND]]
; CHECK-NEXT: [[SUB16:%.*]] = sub nsw <2 x i32> zeroinitializer, [[COND]]
; CHECK-NEXT: [[COND18:%.*]] = select <2 x i1> [[CMP1]], <2 x i32> [[SUB16]], <2 x i32> [[COND]]
; CHECK-NEXT: ret <2 x i32> [[COND18]]
; ;
%sub = sub nsw <2 x i32> zeroinitializer, %x %sub = sub nsw <2 x i32> zeroinitializer, %x
%cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1> %cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
%cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x %cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x
%cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1> %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
%sub16 = sub nsw <2 x i32> zeroinitializer, %cond %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
%cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16 %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16
ret <2 x i32> %cond18 ret <2 x i32> %cond18
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%cond18 = select i1 %cmp1, i32 %sub16, i32 %cond %cond18 = select i1 %cmp1, i32 %sub16, i32 %cond
ret i32 %cond18 ret i32 %cond18
} }
; nabs(nabs(-x)) -> nabs(-x) ; nabs(nabs(-x)) -> nabs(-x)
define <2 x i32> @nabs_nabs_x01_vec(<2 x i32> %x) { define <2 x i32> @nabs_nabs_x01_vec(<2 x i32> %x) {
; CHECK-LABEL: @nabs_nabs_x01_vec( ; CHECK-LABEL: @nabs_nabs_x01_vec(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]] ; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[SUB]], <i32 -1, i32 -1> ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[X]], <2 x i32> [[SUB]] ; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[X]], <2 x i32> [[SUB]]
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt <2 x i32> [[COND]], zeroinitializer ; CHECK-NEXT: ret <2 x i32> [[COND]]
; CHECK-NEXT: [[SUB16:%.*]] = sub nsw <2 x i32> zeroinitializer, [[COND]]
; CHECK-NEXT: [[COND18:%.*]] = select <2 x i1> [[CMP1]], <2 x i32> [[COND]], <2 x i32> [[SUB16]]
; CHECK-NEXT: ret <2 x i32> [[COND18]]
;
; ;
%sub = sub nsw <2 x i32> zeroinitializer, %x %sub = sub nsw <2 x i32> zeroinitializer, %x
%cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1> %cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
%cond = select <2 x i1> %cmp, <2 x i32> %x, <2 x i32> %sub %cond = select <2 x i1> %cmp, <2 x i32> %x, <2 x i32> %sub
%cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1> %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
%sub16 = sub nsw <2 x i32> zeroinitializer, %cond %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
%cond18 = select <2 x i1> %cmp1, <2 x i32> %sub16, <2 x i32> %cond %cond18 = select <2 x i1> %cmp1, <2 x i32> %sub16, <2 x i32> %cond
ret <2 x i32> %cond18 ret <2 x i32> %cond18
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%cond18 = select i1 %cmp1, i32 %cond, i32 %sub16 %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
ret i32 %cond18 ret i32 %cond18
} }
; abs(nabs(-x)) -> abs(-x) ; abs(nabs(-x)) -> abs(-x)
define <2 x i32> @abs_nabs_x01_vec(<2 x i32> %x) { define <2 x i32> @abs_nabs_x01_vec(<2 x i32> %x) {
; CHECK-LABEL: @abs_nabs_x01_vec( ; CHECK-LABEL: @abs_nabs_x01_vec(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]] ; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[SUB]], <i32 -1, i32 -1> ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[X]], <2 x i32> [[SUB]] ; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> [[X]]
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt <2 x i32> [[COND]], zeroinitializer ; CHECK-NEXT: ret <2 x i32> [[COND]]
; CHECK-NEXT: [[SUB16:%.*]] = sub nsw <2 x i32> zeroinitializer, [[COND]]
; CHECK-NEXT: [[COND18:%.*]] = select <2 x i1> [[CMP1]], <2 x i32> [[SUB16]], <2 x i32> [[COND]]
; CHECK-NEXT: ret <2 x i32> [[COND18]]
; ;
%sub = sub nsw <2 x i32> zeroinitializer, %x %sub = sub nsw <2 x i32> zeroinitializer, %x
%cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1> %cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
%cond = select <2 x i1> %cmp, <2 x i32> %x, <2 x i32> %sub %cond = select <2 x i1> %cmp, <2 x i32> %x, <2 x i32> %sub
%cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1> %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
%sub16 = sub nsw <2 x i32> zeroinitializer, %cond %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
%cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16 %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16
ret <2 x i32> %cond18 ret <2 x i32> %cond18
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%cond18 = select i1 %cmp1, i32 %sub16, i32 %cond %cond18 = select i1 %cmp1, i32 %sub16, i32 %cond
ret i32 %cond18 ret i32 %cond18
} }
; nabs(abs(-x)) -> nabs(-x) ; nabs(abs(-x)) -> nabs(-x)
define <2 x i32> @nabs_abs_x01_vec(<2 x i32> %x) { define <2 x i32> @nabs_abs_x01_vec(<2 x i32> %x) {
; CHECK-LABEL: @nabs_abs_x01_vec( ; CHECK-LABEL: @nabs_abs_x01_vec(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]] ; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[SUB]], <i32 -1, i32 -1> ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> [[X]] ; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[X]], <2 x i32> [[SUB]]
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt <2 x i32> [[COND]], zeroinitializer ; CHECK-NEXT: ret <2 x i32> [[COND]]
; CHECK-NEXT: [[SUB16:%.*]] = sub nsw <2 x i32> zeroinitializer, [[COND]]
; CHECK-NEXT: [[COND18:%.*]] = select <2 x i1> [[CMP1]], <2 x i32> [[COND]], <2 x i32> [[SUB16]]
; CHECK-NEXT: ret <2 x i32> [[COND18]]
;
; ;
%sub = sub nsw <2 x i32> zeroinitializer, %x %sub = sub nsw <2 x i32> zeroinitializer, %x
%cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1> %cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
%cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x %cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x
%cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1> %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
%sub16 = sub nsw <2 x i32> zeroinitializer, %cond %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
%cond18 = select <2 x i1> %cmp1, <2 x i32> %sub16, <2 x i32> %cond %cond18 = select <2 x i1> %cmp1, <2 x i32> %sub16, <2 x i32> %cond
ret <2 x i32> %cond18 ret <2 x i32> %cond18
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llvm/trunk/test/Transforms/InstCombine/icmp.ll

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; CHECK-NEXT: [[RES:%.*]] = icmp eq <2 x i8*> %0, zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = icmp eq <2 x i8*> %0, zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[RES]] ; CHECK-NEXT: ret <2 x i1> [[RES]]
; ;
%cast = ptrtoint <2 x i8*> %0 to <2 x i64> %cast = ptrtoint <2 x i8*> %0 to <2 x i64>
%res = icmp eq <2 x i64> %cast, zeroinitializer %res = icmp eq <2 x i64> %cast, zeroinitializer
ret <2 x i1> %res ret <2 x i1> %res
} }
; fold (icmp pred (sub (0, X)) C1) for vec type
define <2 x i32> @Op1Negated_Vec(<2 x i32> %x) {
; CHECK-LABEL: @Op1Negated_Vec(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer
; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> [[X]]
; CHECK-NEXT: ret <2 x i32> [[COND]]
;
%sub = sub nsw <2 x i32> zeroinitializer, %x
%cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
%cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x
ret <2 x i32> %cond
}