[Sparc] Use the IntPair reg class for r constraints with value type f64

[dcederman]

Summary

This is how it appears to be handled in GCC and it prevents a "Unknown mismatch" error in the SelectionDAGBuilder.

[jyknight]

Yep, this looks like the expected behavior.

[jrtc27]

What happens to this test case on sparc64? Does something else complain earlier that "r" shouldn't be used for floats, or does it try to use a pair of "32-bit" integer registers even though they're 64-bit?

[jrtc27]

It turns out the backend just doesn't support 64-bit integer registers in assembly constraints on sparc64 anyway, so this doesn't make it any worse. I have a local patch which I will prepare and submit once this lands.

lib/Target/Sparc/SparcISelLowering.cpp

 
 std::pair<unsigned, const TargetRegisterClass *>
 SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                                   StringRef Constraint,
                                                   MVT VT) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     case 'r':
-      if (VT == MVT::v2i32)
+      if (VT == MVT::v2i32 || VT == MVT::f64)
         return std::make_pair(0U, &SP::IntPairRegClass);
       else
         return std::make_pair(0U, &SP::IntRegsRegClass);
     case 'f':
       if (VT == MVT::f32)
         return std::make_pair(0U, &SP::FPRegsRegClass);
       else if (VT == MVT::f64)
         return std::make_pair(0U, &SP::LowDFPRegsRegClass);

test/CodeGen/SPARC/inlineasm.ll

 ; CHECK: fadds %f20, %f20, %f20
 ; CHECK: faddd %f20, %f20, %f20
 define void @test_constraint_float_reg() {
 entry:
   tail call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"(float 6.0, float 7.0, float 8.0)
   tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, double 11.0)
   ret void
 }
+
+; CHECK-LABEL: test_constraint_r_f64:
+; CHECK: std %o0, [%sp+96]
+; CHECK: ldd [%sp+96], %f0
+define double @test_constraint_r_f64() {
+entry:
+  %0 = call double asm sideeffect "", "=r"()
+  ret double %0
+}