RenameIndependentSubregs: Fix handling of undef tied operands

[msearles]

Summary

Ensure that, if updating a tied operand pair, to only update that pair.

[arsenm]

LGTM

lib/CodeGen/RenameIndependentSubregs.cpp

void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes,
   const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
   unsigned Reg = Intervals[0]->reg;
   for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg),
        E = MRI->reg_nodbg_end(); I != E; ) {
     MachineOperand &MO = *I++;
     if (!MO.isDef() && !MO.readsReg())
       continue;
 
-    SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());
+    auto *MI = MO.getParent();
+    SlotIndex Pos = LIS->getInstructionIndex(*MI);
     Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
                      : Pos.getBaseIndex();
     unsigned SubRegIdx = MO.getSubReg();
     LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
 
     unsigned ID = ~0u;
     for (const SubRangeInfo &SRInfo : SubRangeInfos) {
       const LiveInterval::SubRange &SR = *SRInfo.SR;
for (const SubRangeInfo &SRInfo : SubRangeInfos) {
       ID = Classes[LocalID + SRInfo.Index];
       break;
     }
 
     unsigned VReg = Intervals[ID]->reg;
     MO.setReg(VReg);
 
     if (MO.isTied() && Reg != VReg) {
-      /// Undef use operands are not tracked in the equivalence class but need
-      /// to be update if they are tied.
-      MO.getParent()->substituteRegister(Reg, VReg, 0, TRI);
+      /// Undef use operands are not tracked in the equivalence class,
+      /// but need to be updated if they are tied; take care to only
+      /// update the tied operand.
+      unsigned OperandNo = MI->getOperandNo(&MO);
+      unsigned TiedIdx = MI->findTiedOperandIdx(OperandNo);
+      MI->getOperand(TiedIdx).setReg(VReg);
 
-      // substituteRegister breaks the iterator, so restart.
+      // above substitution breaks the iterator, so restart.
       I = MRI->reg_nodbg_begin(Reg);
     }
   }
   // TODO: We could attempt to recompute new register classes while visiting
   // the operands: Some of the split register may be fine with less constraint
   // classes than the original vreg.
 }
 

test/CodeGen/AMDGPU/rename-independent-subregs.mir

 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass simple-register-coalescing,rename-independent-subregs -o - %s | FileCheck %s
 --- |
   define amdgpu_kernel void @test0() { ret void }
   define amdgpu_kernel void @test1() { ret void }
+  define amdgpu_kernel void @test2() { ret void }
 ...
 ---
 # In the test below we have two independent def+use pairs of subregister1 which
 # can be moved to a new virtual register. The third def of sub1 however is used
 # in combination with sub0 and needs to stay with the original vreg.
 # CHECK-LABEL: name: test0
 # CHECK: S_NOP 0, implicit-def undef %0.sub0
 # CHECK: S_NOP 0, implicit-def undef %2.sub1
bb.1:
     S_NOP 0, implicit-def %1.sub0
     S_NOP 0, implicit %1.sub1
     S_NOP 0, implicit %1.sub0
 
   bb.2:
     S_NOP 0, implicit %0.sub2
 
 ...
+# In this test, there are two pairs of tied operands
+# within the inline asm statement:
+# (1) %0.sub0 + %0.sub0 and (2) %0.sub1 + %0.sub1
+# Check that renaming (2) does not inadvertently rename (1).
+# CHECK-LABEL: name: test2
+# CHECK: INLINEASM &"", 32, 327690, def undef %0.sub0, 327690, def dead %1.sub1, 2147483657, undef %0.sub0(tied-def 3), 2147549193, %1.sub1(tied-def 5)
+name: test2
+body: |
+  bb.0:
+    undef %0.sub0:vreg_64 = IMPLICIT_DEF
+
+  bb.1:
+    undef %0.sub1:vreg_64 = V_ALIGNBIT_B32 %0.sub0:vreg_64, %0.sub0:vreg_64, 16, implicit $exec
+    INLINEASM &"", 32, 327690, def undef %0.sub0:vreg_64, 327690, def %0.sub1:vreg_64, 2147483657, undef %0.sub0:vreg_64(tied-def 3), 2147549193, %0.sub1:vreg_64(tied-def 5)
+    S_BRANCH %bb.1
+
+...