[X86][BtVer2][NFC] Regexify zero-idioms

[RKSimon]

Please don't use regexes unless you really need to - its a little difficult to gauge but in general these take a LOT longer on tblgen - they only really work well if you don't start with a pattern so InstRegexOp::apply can reduce the search range considerably.

[lebedev.ri]

In D48878#1150823, @RKSimon wrote:

Please don't use regexes unless you really need to - its a little difficult to gauge but in general these take a LOT longer on tblgen - they only really work well if you don't start with a pattern so InstRegexOp::apply can reduce the search range considerably.

Interesting, unfortunate. Ok, good to know!

lib/Target/X86/X86ScheduleBtVer2.td

 // 15h Processors".
 // Reference: Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
 // Section 21.8 [Dependency-breaking instructions].
 
 def JWriteZeroIdiom : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
     SchedVar<MCSchedPredicate<TruePred>,           [WriteALU]>
 ]>;
-def : InstRW<[JWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
-                                        XOR32rr, XOR64rr)>;
+def : InstRW<[JWriteZeroIdiom], (instregex "(SUB|XOR)(32|64)rr")>;
 
 def JWriteFZeroIdiom : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
     SchedVar<MCSchedPredicate<TruePred>,           [WriteFLogic]>
 ]>;
-def : InstRW<[JWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, VXORPDrr,
-                                         ANDNPSrr, VANDNPSrr,
-                                         ANDNPDrr, VANDNPDrr)>;
+def : InstRW<[JWriteFZeroIdiom], (instregex "(V?)(XOR|ANDN)P(S|D)rr")>;
 
 def JWriteVZeroIdiomLogic : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
     SchedVar<MCSchedPredicate<TruePred>,           [WriteVecLogic]>
 ]>;
-def : InstRW<[JWriteVZeroIdiomLogic], (instrs MMX_PXORirr, MMX_PANDNirr)>;
+def : InstRW<[JWriteVZeroIdiomLogic], (instregex "MMX_P(XOR|ANDN)irr")>;
 
 def JWriteVZeroIdiomLogicX : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
     SchedVar<MCSchedPredicate<TruePred>,           [WriteVecLogicX]>
 ]>;
-def : InstRW<[JWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr,
-                                               PANDNrr, VPANDNrr)>;
+def : InstRW<[JWriteVZeroIdiomLogicX], (instregex "(V?)P(XOR|ANDN)rr")>;
 
 def JWriteVZeroIdiomALU : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
     SchedVar<MCSchedPredicate<TruePred>,           [WriteVecALU]>
 ]>;
-def : InstRW<[JWriteVZeroIdiomALU], (instrs MMX_PSUBBirr, MMX_PSUBDirr,
-                                            MMX_PSUBQirr, MMX_PSUBWirr,
-                                            MMX_PCMPEQBirr,
-                                            MMX_PCMPEQDirr,
-                                            MMX_PCMPEQWirr,
-                                            MMX_PCMPGTBirr,
-                                            MMX_PCMPGTDirr,
-                                            MMX_PCMPGTWirr)>;
+def : InstRW<[JWriteVZeroIdiomALU],  (instregex "MMX_P(SUB(B|D|Q|W)|(CMP(EQ|GT)(B|D|W)))irr")>;
 
 def JWriteVZeroIdiomALUX : SchedWriteVariant<[
     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
     SchedVar<MCSchedPredicate<TruePred>,           [WriteVecALUX]>
 ]>;
-def : InstRW<[JWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
-                                             PSUBDrr, VPSUBDrr,
-                                             PSUBQrr, VPSUBQrr,
-                                             PSUBWrr, VPSUBWrr,
-                                             PCMPEQBrr, VPCMPEQBrr,
-                                             PCMPEQDrr, VPCMPEQDrr,
-                                             PCMPEQQrr, VPCMPEQQrr,
-                                             PCMPEQWrr, VPCMPEQWrr,
-                                             PCMPGTBrr, VPCMPGTBrr,
-                                             PCMPGTDrr, VPCMPGTDrr,
-                                             PCMPGTQrr, VPCMPGTQrr,
-                                             PCMPGTWrr, VPCMPGTWrr)>;
+def : InstRW<[JWriteVZeroIdiomALUX], (instregex "(V?)P(SUB(B|D|Q|W)|(CMP(EQ|GT)(B|D|Q|W)))rr")>;
+
 } // SchedModel