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[Mips][FastISel] Do not duplicate condition while lowering branches
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Authored by draganm on Jun 27 2018, 6:08 AM.

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Summary

This change fixes the issue that arises when we duplicate condition from the predecessor block. If the condition's arguments are not considered alive across the blocks, fast regalloc gets confused and starts generating reloads from the slots that have never been spilled to. This change also leads to smaller code given that, unlike on architectures with condition codes, on Mips we can branch directly on register value, thus we gain nothing by duplication.

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rL LLVM

Event Timeline

draganm created this revision.Jun 27 2018, 6:08 AM
This revision is now accepted and ready to land.Jun 28 2018, 8:02 AM
draganm added a subscriber: petarj.Jun 28 2018, 8:20 AM
draganm retitled this revision from [Mips][FastISel] Do not duplicate compare condition when lowering conditional branches to [Mips][FastISel] Do not duplicate condition while lowering branches.Jul 2 2018, 1:50 AM
draganm edited the summary of this revision. (Show Details)
This revision was automatically updated to reflect the committed changes.