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Differential D48637

[Sparc] Generate ta 1 for the @llvm.debugtrap intrinsic
ClosedPublic

Authored by dcederman on Jun 27 2018, 5:27 AM.

Details

Reviewers
jyknight
venkatra
Commits
rG68765757d4e9: [Sparc] Generate ta 1 for the @llvm.debugtrap intrinsic
rL337163: [Sparc] Generate ta 1 for the @llvm.debugtrap intrinsic
Summary

Software trap number one is the trap used for breakpoints in the Sparc ABI.

Diff Detail

Event Timeline

dcederman created this revision.Jun 27 2018, 5:27 AM
Herald added subscribers: llvm-commits, jrtc27, fedor.sergeev. · View Herald TranscriptJun 27 2018, 5:27 AM
jyknight accepted this revision.Jul 13 2018, 11:40 AM
This revision is now accepted and ready to land.Jul 13 2018, 11:40 AM
Closed by commit rL337163: [Sparc] Generate ta 1 for the @llvm.debugtrap intrinsic (authored by dcederman). · Explain WhyJul 16 2018, 5:22 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Sparc/
1 line
3 lines
test/
CodeGen/
SPARC/
10 lines

Diff 153052

lib/Target/Sparc/SparcISelLowering.cpp

Show First 20 Lines • Show All 1,721 Lines • ▼ Show 20 LinesSparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
} }
// VASTART needs to be custom lowered to use the VarArgsFrameIndex. // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
setOperationAction(ISD::VASTART , MVT::Other, Custom); setOperationAction(ISD::VASTART , MVT::Other, Custom);
// VAARG needs to be lowered to not do unaligned accesses for doubles. // VAARG needs to be lowered to not do unaligned accesses for doubles.
setOperationAction(ISD::VAARG , MVT::Other, Custom); setOperationAction(ISD::VAARG , MVT::Other, Custom);
setOperationAction(ISD::TRAP , MVT::Other, Legal); setOperationAction(ISD::TRAP , MVT::Other, Legal);
setOperationAction(ISD::DEBUGTRAP , MVT::Other, Legal);
// Use the default implementation. // Use the default implementation.
setOperationAction(ISD::VACOPY , MVT::Other, Expand); setOperationAction(ISD::VACOPY , MVT::Other, Expand);
setOperationAction(ISD::VAEND , MVT::Other, Expand); setOperationAction(ISD::VAEND , MVT::Other, Expand);
setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
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lib/Target/Sparc/SparcInstrInfo.td

Show First 20 Lines • Show All 1,003 Lines • ▼ Show 20 Lines
let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
defm TICC : TRAP<"%icc">; defm TICC : TRAP<"%icc">;
let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>; def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
def : Pat<(debugtrap),
(TRAPri (i32 G0), (i32 1), (i32 8))>;
// Section B.28 - Read State Register Instructions // Section B.28 - Read State Register Instructions
let rs2 = 0 in let rs2 = 0 in
def RDASR : F3_1<2, 0b101000, def RDASR : F3_1<2, 0b101000,
(outs IntRegs:$rd), (ins ASRRegs:$rs1), (outs IntRegs:$rd), (ins ASRRegs:$rs1),
"rd $rs1, $rd", []>; "rd $rs1, $rd", []>;
// PSR, WIM, and TBR don't exist on the SparcV9, only the V8. // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
let Predicates = [HasNoV9] in { let Predicates = [HasNoV9] in {
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test/CodeGen/SPARC/trap.ll

; RUN: llc -mtriple=sparc-linux-gnu < %s -show-mc-encoding | FileCheck %s ; RUN: llc -mtriple=sparc-linux-gnu < %s -show-mc-encoding | FileCheck %s
define void @test1() { define void @test1() {
tail call void @llvm.trap() tail call void @llvm.trap()
unreachable unreachable
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: ta 5 ! encoding: [0x91,0xd0,0x20,0x05] ; CHECK: ta 5 ! encoding: [0x91,0xd0,0x20,0x05]
} }
declare void @llvm.trap() declare void @llvm.trap()
; CHECK-LABEL: testdebugtrap:
; CHECK: ta 1 ! encoding: [0x91,0xd0,0x20,0x01]
define void @testdebugtrap() {
entry:
call void @llvm.debugtrap()
ret void
}
declare void @llvm.debugtrap()