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Differential D48595

Avoid losing Hi part when expanding VAARG nodes on big endian machines
ClosedPublic

Authored by dcederman on Jun 26 2018, 8:29 AM.

Details

Reviewers
jyknight
Commits
rGc3d8002c2e1b: Avoid losing Hi part when expanding VAARG nodes on big endian machines
rL337161: Avoid losing Hi part when expanding VAARG nodes on big endian machines
Summary

If the high part of the load is not used the offset to the next element will not be set correctly.

For example, on Sparc V8, the following code will read val2 from offset 4 instead of 8.

int val = __builtin_va_arg(va, long long);
int val2 = __builtin_va_arg(va, int);

Diff Detail

Event Timeline

dcederman created this revision.Jun 26 2018, 8:29 AM
Herald added subscribers: llvm-commits, jrtc27, fedor.sergeev. · View Herald TranscriptJun 26 2018, 8:29 AM
jyknight accepted this revision.Jul 13 2018, 11:32 AM

Chain bugs are evil. =)

This revision is now accepted and ready to land.Jul 13 2018, 11:32 AM
Closed by commit rL337161: Avoid losing Hi part when expanding VAARG nodes on big endian machines (authored by dcederman). · Explain WhyJul 16 2018, 5:19 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
CodeGen/
SelectionDAG/
3 lines
test/
CodeGen/
SPARC/
24 lines

Diff 152895

lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp

Show First 20 Lines • Show All 294 Lines • ▼ Show 20 Linesvoid DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
SDValue Chain = N->getOperand(0); SDValue Chain = N->getOperand(0);
SDValue Ptr = N->getOperand(1); SDValue Ptr = N->getOperand(1);
SDLoc dl(N); SDLoc dl(N);
const unsigned Align = N->getConstantOperandVal(3); const unsigned Align = N->getConstantOperandVal(3);
Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2), Align); Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2), Align);
Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, N->getOperand(2), 0); Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, N->getOperand(2), 0);
Chain = Hi.getValue(1);
// Handle endianness of the load. // Handle endianness of the load.
if (TLI.hasBigEndianPartOrdering(OVT, DAG.getDataLayout())) if (TLI.hasBigEndianPartOrdering(OVT, DAG.getDataLayout()))
std::swap(Lo, Hi); std::swap(Lo, Hi);
// Modified the chain - switch anything that used the old chain to use // Modified the chain - switch anything that used the old chain to use
// the new one. // the new one.
ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); ReplaceValueWith(SDValue(N, 1), Chain);
} }
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// Generic Operand Expansion. // Generic Operand Expansion.
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
void DAGTypeLegalizer::IntegerToVector(SDValue Op, unsigned NumElements, void DAGTypeLegalizer::IntegerToVector(SDValue Op, unsigned NumElements,
▲ Show 20 Lines • Show All 257 Lines • Show Last 20 Lines

test/CodeGen/SPARC/varargs-v8.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=sparc -disable-sparc-leaf-proc | FileCheck %s
define i32 @test(i32 %a, i8* %va) nounwind {
; CHECK-LABEL: test:
; CHECK: ! %bb.0: ! %entry
; CHECK-NEXT: save %sp, -96, %sp
; CHECK-NEXT: add %i1, 8, %i0
; CHECK-NEXT: st %i0, [%fp+-4]
; CHECK-NEXT: ld [%i1+4], %i0
; CHECK-NEXT: add %i1, 12, %i2
; CHECK-NEXT: st %i2, [%fp+-4]
; CHECK-NEXT: ld [%i1+8], %i1
; CHECK-NEXT: ret
; CHECK-NEXT: restore %i1, %i0, %o0
entry:
%va.addr = alloca i8*, align 4
store i8* %va, i8** %va.addr, align 4
%0 = va_arg i8** %va.addr, i64
%conv1 = trunc i64 %0 to i32
%1 = va_arg i8** %va.addr, i32
%add3 = add nsw i32 %1, %conv1
ret i32 %add3
}