[llvm-exegesis] Add partial X87 support.

[courbet]

Summary

This enables the X86-specific X86FloatingPointStackifierPass, and allow
llvm-exegesis to generate and measure X87 latency/uops for some FP ops.

[gchatelet]

tools/llvm-exegesis/lib/BenchmarkRunner.cpp

201 ↗

(On Diff #152873)

As discussed, let's create SelfAliasing in the function so we don't rely on the caller to do the right thing.

tools/llvm-exegesis/lib/Latency.cpp

94 ↗

(On Diff #152873)

Let's do the following:

auto result = generateSelfAliasingPrototype(Instr);
if(result is ok) return result;
return generateTwoInstructionPrototype(Instr);

[courbet]

address review comments

[gchatelet]

tools/llvm-exegesis/lib/BenchmarkRunner.cpp

201 ↗

(On Diff #153037)

Move just above the if (where it's used)

203 ↗

(On Diff #153037)

Move below if (SelfAliasing.empty()) block.

tools/llvm-exegesis/lib/Latency.cpp

92 ↗

(On Diff #153037)

this is not needed it you use the llvm idiom

if(auto SelfAliasingPrototype = generateSelfAliasingPrototype(Instr)) {
   return SelfAliasingPrototype;
}

[courbet]

tools/llvm-exegesis/lib/Latency.cpp

92 ↗

(On Diff #153037)

Unfortunately this does not work as is leaves the error unchecked.

[courbet]

address review comments

[courbet]

better scoping

[courbet]

Use BenchmarkFailure instead of llvm::StringError

llvm/trunk/tools/llvm-exegesis/lib/BenchmarkRunner.h

public:
   // Given a snippet, computes which registers the setup code needs to define.
   std::vector<unsigned>
   computeRegsToDef(const std::vector<InstructionInstance> &Snippet) const;
 
 protected:
   const LLVMState &State;
   const RegisterAliasingTrackerCache RATC;
 
+  llvm::Expected<SnippetPrototype> generateSelfAliasingPrototype(
+      const Instruction &Instr) const;
+
 private:
   // API to be implemented by subclasses.
   virtual llvm::Expected<SnippetPrototype>
     generatePrototype(unsigned Opcode) const = 0;
 
   virtual std::vector<BenchmarkMeasure>
     runMeasurements(const ExecutableFunction &EF,
                     const unsigned NumRepetitions) const = 0;

llvm/trunk/tools/llvm-exegesis/lib/BenchmarkRunner.cpp

if (llvm::Error E = llvm::errorCodeToError(llvm::sys::fs::createTemporaryFile(
           "snippet", "o", ResultFD, ResultPath)))
     return std::move(E);
   llvm::raw_fd_ostream OFS(ResultFD, true /*ShouldClose*/);
   assembleToStream(State.getExegesisTarget(), State.createTargetMachine(),
                    Setup.RegsToDef, Code, OFS);
   return ResultPath.str();
 }
 
+llvm::Expected<SnippetPrototype> BenchmarkRunner::generateSelfAliasingPrototype(
+    const Instruction &Instr) const {
+  const AliasingConfigurations SelfAliasing(Instr, Instr);
+  if (SelfAliasing.empty()) {
+    return llvm::make_error<BenchmarkFailure>("empty self aliasing");
+  }
+  SnippetPrototype Prototype;
+  InstructionInstance II(Instr);
+  if (SelfAliasing.hasImplicitAliasing()) {
+    Prototype.Explanation = "implicit Self cycles, picking random values.";
+  } else {
+    Prototype.Explanation =
+        "explicit self cycles, selecting one aliasing Conf.";
+    // This is a self aliasing instruction so defs and uses are from the same
+    // instance, hence twice II in the following call.
+    setRandomAliasing(SelfAliasing, II, II);
+  }
+  Prototype.Snippet.push_back(std::move(II));
+  return std::move(Prototype);
+}
+
 } // namespace exegesis

llvm/trunk/tools/llvm-exegesis/lib/Latency.h

public:
   ~LatencyBenchmarkRunner() override;
 
   llvm::Expected<SnippetPrototype>
   generatePrototype(unsigned Opcode) const override;
 
 private:
   llvm::Error isInfeasible(const llvm::MCInstrDesc &MCInstrDesc) const;
 
-  llvm::Expected<SnippetPrototype> generateSelfAliasingPrototype(
-      const Instruction &Instr,
-      const AliasingConfigurations &SelfAliasing) const;
-
   llvm::Expected<SnippetPrototype> generateTwoInstructionPrototype(
-      const Instruction &Instr,
-      const AliasingConfigurations &SelfAliasing) const;
+      const Instruction &Instr) const;
 
   std::vector<BenchmarkMeasure>
   runMeasurements(const ExecutableFunction &EF,
                   const unsigned NumRepetitions) const override;
 };
 
 } // namespace exegesis
 
 #endif // LLVM_TOOLS_LLVM_EXEGESIS_LATENCY_H

llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp

return llvm::make_error<BenchmarkFailure>(
         "Infeasible : has unknown operands");
   if (llvm::any_of(MCInstrDesc.operands(), hasMemoryOperand))
     return llvm::make_error<BenchmarkFailure>(
         "Infeasible : has memory operands");
   return llvm::Error::success();
 }
 
 llvm::Expected<SnippetPrototype>
-LatencyBenchmarkRunner::generateSelfAliasingPrototype(
-    const Instruction &Instr,
-    const AliasingConfigurations &SelfAliasing) const {
-  SnippetPrototype Prototype;
-  InstructionInstance II(Instr);
-  if (SelfAliasing.hasImplicitAliasing()) {
-    Prototype.Explanation = "implicit Self cycles, picking random values.";
-  } else {
-    Prototype.Explanation =
-        "explicit self cycles, selecting one aliasing Conf.";
-    // This is a self aliasing instruction so defs and uses are from the same
-    // instance, hence twice II in the following call.
-    setRandomAliasing(SelfAliasing, II, II);
-  }
-  Prototype.Snippet.push_back(std::move(II));
-  return std::move(Prototype);
-}
-
-llvm::Expected<SnippetPrototype>
 LatencyBenchmarkRunner::generateTwoInstructionPrototype(
-    const Instruction &Instr,
-    const AliasingConfigurations &SelfAliasing) const {
+    const Instruction &Instr) const {
   std::vector<unsigned> Opcodes;
   Opcodes.resize(State.getInstrInfo().getNumOpcodes());
   std::iota(Opcodes.begin(), Opcodes.end(), 0U);
   std::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator());
   for (const unsigned OtherOpcode : Opcodes) {
     if (OtherOpcode == Instr.Description->Opcode)
       continue;
     const auto &OtherInstrDesc = State.getInstrInfo().get(OtherOpcode);
     if (auto E = isInfeasible(OtherInstrDesc)) {
       llvm::consumeError(std::move(E));
       continue;
     }
     const Instruction OtherInstr(OtherInstrDesc, RATC);
     const AliasingConfigurations Forward(Instr, OtherInstr);
     const AliasingConfigurations Back(OtherInstr, Instr);
     if (Forward.empty() || Back.empty())
       continue;
     InstructionInstance ThisII(Instr);
     InstructionInstance OtherII(OtherInstr);
     if (!Forward.hasImplicitAliasing())
       setRandomAliasing(Forward, ThisII, OtherII);
     if (!Back.hasImplicitAliasing())
       setRandomAliasing(Back, OtherII, ThisII);
     SnippetPrototype Prototype;
-    Prototype.Explanation = llvm::formatv("creating cycle through {0}.",
-                                          State.getInstrInfo().getName(OtherOpcode));
+    Prototype.Explanation =
+        llvm::formatv("creating cycle through {0}.",
     Prototype.Snippet.push_back(std::move(ThisII));
     Prototype.Snippet.push_back(std::move(OtherII));
     return std::move(Prototype);
   }
   return llvm::make_error<BenchmarkFailure>(
       "Infeasible : Didn't find any scheme to make the instruction serial");
 }
 
 llvm::Expected<SnippetPrototype>
 LatencyBenchmarkRunner::generatePrototype(unsigned Opcode) const {
   const auto &InstrDesc = State.getInstrInfo().get(Opcode);
   if (auto E = isInfeasible(InstrDesc))
     return std::move(E);
   const Instruction Instr(InstrDesc, RATC);
-  const AliasingConfigurations SelfAliasing(Instr, Instr);
-  if (SelfAliasing.empty()) {
-    // No self aliasing, trying to create a dependency through another opcode.
-    return generateTwoInstructionPrototype(Instr, SelfAliasing);
-  } else {
-    return generateSelfAliasingPrototype(Instr, SelfAliasing);
-  }
+  if (auto SelfAliasingPrototype = generateSelfAliasingPrototype(Instr))
+    return SelfAliasingPrototype;
+  else
+    llvm::consumeError(SelfAliasingPrototype.takeError());
+  return generateTwoInstructionPrototype(Instr);
 }
 
 std::vector<BenchmarkMeasure>
 LatencyBenchmarkRunner::runMeasurements(const ExecutableFunction &Function,
                                         const unsigned NumRepetitions) const {
   // Cycle measurements include some overhead from the kernel. Repeat the
   // measure several times and take the minimum value.
   constexpr const int NumMeasurements = 30;

llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp

 //===-- Target.cpp ----------------------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 #include "../Target.h"
 
 #include "../Latency.h"
 #include "../Uops.h"
+#include "MCTargetDesc/X86BaseInfo.h"
 #include "MCTargetDesc/X86MCTargetDesc.h"
 #include "X86.h"
 #include "X86RegisterInfo.h"
 #include "llvm/MC/MCInstBuilder.h"
 
 namespace exegesis {
 
+namespace {
+
+// Common code for X86 Uops and Latency runners.
+template <typename Impl> class X86BenchmarkRunner : public Impl {
+  using Impl::Impl;
+
+  llvm::Expected<SnippetPrototype>
+  generatePrototype(unsigned Opcode) const override {
     // Test whether we can generate a snippet for this instruction.
-static llvm::Error shouldRun(const LLVMState &State, const unsigned Opcode) {
-  const auto &InstrInfo = State.getInstrInfo();
+    const auto &InstrInfo = this->State.getInstrInfo();
     const auto OpcodeName = InstrInfo.getName(Opcode);
     if (OpcodeName.startswith("POPF") || OpcodeName.startswith("PUSHF") ||
         OpcodeName.startswith("ADJCALLSTACK")) {
       return llvm::make_error<BenchmarkFailure>(
           "Unsupported opcode: Push/Pop/AdjCallStack");
     }
-  return llvm::ErrorSuccess();
-}
 
-namespace {
+    // Handle X87.
+    const auto &InstrDesc = InstrInfo.get(Opcode);
+    const unsigned FPInstClass = InstrDesc.TSFlags & llvm::X86II::FPTypeMask;
+    const Instruction Instr(InstrDesc, this->RATC);
+    switch (FPInstClass) {
+    case llvm::X86II::NotFP:
+      break;
+    case llvm::X86II::ZeroArgFP:
+      return Impl::handleZeroArgFP(Instr);
+    case llvm::X86II::OneArgFP:
+      return Impl::handleOneArgFP(Instr); // fstp ST(0)
+    case llvm::X86II::OneArgFPRW:
+    case llvm::X86II::TwoArgFP: {
+      // These are instructions like
+      //   - `ST(0) = fsqrt(ST(0))` (OneArgFPRW)
+      //   - `ST(0) = ST(0) + ST(i)` (TwoArgFP)
+      // They are intrinsically serial and do not modify the state of the stack.
+      // We generate the same code for latency and uops.
+      return this->generateSelfAliasingPrototype(Instr);
+    }
+    case llvm::X86II::CompareFP:
+      return Impl::handleCompareFP(Instr);
+    case llvm::X86II::CondMovFP:
+      return Impl::handleCondMovFP(Instr);
+    case llvm::X86II::SpecialFP:
+      return Impl::handleSpecialFP(Instr);
+    default:
+      llvm_unreachable("Unknown FP Type!");
+    }
 
-class X86LatencyBenchmarkRunner : public LatencyBenchmarkRunner {
-private:
-  using LatencyBenchmarkRunner::LatencyBenchmarkRunner;
+    // Fallback to generic implementation.
+    return Impl::Base::generatePrototype(Opcode);
+  }
+};
 
+class X86LatencyImpl : public LatencyBenchmarkRunner {
+protected:
+  using Base = LatencyBenchmarkRunner;
+  using Base::Base;
   llvm::Expected<SnippetPrototype>
-  generatePrototype(unsigned Opcode) const override {
-    if (llvm::Error E = shouldRun(State, Opcode)) {
-      return std::move(E);
-    }
-    return LatencyBenchmarkRunner::generatePrototype(Opcode);
+  handleZeroArgFP(const Instruction &Instr) const {
+    return llvm::make_error<BenchmarkFailure>("Unsupported x87 ZeroArgFP");
+  }
+  llvm::Expected<SnippetPrototype>
+  handleOneArgFP(const Instruction &Instr) const {
+    return llvm::make_error<BenchmarkFailure>("Unsupported x87 OneArgFP");
+  }
+  llvm::Expected<SnippetPrototype>
+  handleCompareFP(const Instruction &Instr) const {
+    return llvm::make_error<BenchmarkFailure>("Unsupported x87 CompareFP");
+  }
+  llvm::Expected<SnippetPrototype>
+  handleCondMovFP(const Instruction &Instr) const {
+    return llvm::make_error<BenchmarkFailure>("Unsupported x87 CondMovFP");
+  llvm::Expected<SnippetPrototype>
+  handleSpecialFP(const Instruction &Instr) const {
+    return llvm::make_error<BenchmarkFailure>("Unsupported x87 SpecialFP");
   }
 };
 
-class X86UopsBenchmarkRunner : public UopsBenchmarkRunner {
-private:
-  using UopsBenchmarkRunner::UopsBenchmarkRunner;
-
+class X86UopsImpl : public UopsBenchmarkRunner {
+protected:
+  using Base = UopsBenchmarkRunner;
+  using Base::Base;
   llvm::Expected<SnippetPrototype>
-  generatePrototype(unsigned Opcode) const override {
-    if (llvm::Error E = shouldRun(State, Opcode)) {
-      return std::move(E);
-    }
-    return UopsBenchmarkRunner::generatePrototype(Opcode);
+  handleZeroArgFP(const Instruction &Instr) const {
+    return llvm::make_error<BenchmarkFailure>("Unsupported x87 ZeroArgFP");
+  llvm::Expected<SnippetPrototype>
+  handleOneArgFP(const Instruction &Instr) const {
+    return llvm::make_error<BenchmarkFailure>("Unsupported x87 OneArgFP");
+  }
+  llvm::Expected<SnippetPrototype>
+  handleCompareFP(const Instruction &Instr) const {
+    return llvm::make_error<BenchmarkFailure>("Unsupported x87 CompareFP");
+  }
+  llvm::Expected<SnippetPrototype>
+  handleCondMovFP(const Instruction &Instr) const {
+    return llvm::make_error<BenchmarkFailure>("Unsupported x87 CondMovFP");
+  }
+  llvm::Expected<SnippetPrototype>
+  handleSpecialFP(const Instruction &Instr) const {
+    return llvm::make_error<BenchmarkFailure>("Unsupported x87 SpecialFP");
   }
 };
 
 class ExegesisX86Target : public ExegesisTarget {
   void addTargetSpecificPasses(llvm::PassManagerBase &PM) const override {
     // Lowers FP pseudo-instructions, e.g. ABS_Fp32 -> ABS_F.
     // FIXME: Enable when the exegesis assembler no longer does
     // Properties.reset(TracksLiveness);
-    // PM.add(llvm::createX86FloatingPointStackifierPass());
+    PM.add(llvm::createX86FloatingPointStackifierPass());
   }
 
   std::vector<llvm::MCInst>
   setRegToConstant(unsigned Reg) const override {
-    // FIXME: Handle FP stack:
-    // llvm::X86::RFP32RegClass
-    // llvm::X86::RFP64RegClass
-    // llvm::X86::RFP80RegClass
     if (llvm::X86::GR8RegClass.contains(Reg)) {
       return {llvm::MCInstBuilder(llvm::X86::MOV8ri).addReg(Reg).addImm(1)};
     }
     if (llvm::X86::GR16RegClass.contains(Reg)) {
       return {llvm::MCInstBuilder(llvm::X86::MOV16ri).addReg(Reg).addImm(1)};
     }
     if (llvm::X86::GR32RegClass.contains(Reg)) {
       return {llvm::MCInstBuilder(llvm::X86::MOV32ri).addReg(Reg).addImm(1)};
     }
     if (llvm::X86::GR64RegClass.contains(Reg)) {
       return {llvm::MCInstBuilder(llvm::X86::MOV64ri32).addReg(Reg).addImm(1)};
     }
     if (llvm::X86::VR128XRegClass.contains(Reg)) {
       return setVectorRegToConstant(Reg, 16, llvm::X86::VMOVDQUrm);
     }
     if (llvm::X86::VR256XRegClass.contains(Reg)) {
       return setVectorRegToConstant(Reg, 32, llvm::X86::VMOVDQUYrm);
     }
     if (llvm::X86::VR512RegClass.contains(Reg)) {
       return setVectorRegToConstant(Reg, 64, llvm::X86::VMOVDQU64Zrm);
     }
+    if (llvm::X86::RFP32RegClass.contains(Reg) ||
+        llvm::X86::RFP64RegClass.contains(Reg) ||
+        llvm::X86::RFP80RegClass.contains(Reg)) {
+      return setVectorRegToConstant(Reg, 8, llvm::X86::LD_Fp64m);
+    }
     return {};
   }
 
   std::unique_ptr<BenchmarkRunner>
   createLatencyBenchmarkRunner(const LLVMState &State) const override {
-    return llvm::make_unique<X86LatencyBenchmarkRunner>(State);
+    return llvm::make_unique<X86BenchmarkRunner<X86LatencyImpl>>(
+        State);
   }
 
   std::unique_ptr<BenchmarkRunner>
   createUopsBenchmarkRunner(const LLVMState &State) const override {
-    return llvm::make_unique<X86UopsBenchmarkRunner>(State);
+    return llvm::make_unique<X86BenchmarkRunner<X86UopsImpl>>(State);
   }
 
   bool matchesArch(llvm::Triple::ArchType Arch) const override {
     return Arch == llvm::Triple::x86_64 || Arch == llvm::Triple::x86;
   }
 
 private:
   // setRegToConstant() specialized for a vector register of size