[Hexagon] Add a "generic" processor

[bcahoon]

Summary

The generic processor is added to be used with a 3rd party program that create a back-end with the "generic" CPU. This patch also enables the JIT for Hexagon.

[kparzysz]

Committed in rL335641.

llvm/lib/Target/Hexagon/Hexagon.td

 //===----------------------------------------------------------------------===//
 // Hexagon processors supported.
 //===----------------------------------------------------------------------===//
 
 class Proc<string Name, SchedMachineModel Model,
            list<SubtargetFeature> Features>
  : ProcessorModel<Name, Model, Features>;
 
+def : Proc<"generic", HexagonModelV60,
+           [ArchV4, ArchV5, ArchV55, ArchV60,
+            FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
+            FeaturePackets, FeatureSmallData]>;
 def : Proc<"hexagonv4",  HexagonModelV4,
            [ArchV4,
             FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
             FeaturePackets, FeatureSmallData]>;
 def : Proc<"hexagonv5",  HexagonModelV4,
            [ArchV4, ArchV5,
             FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
             FeaturePackets, FeatureSmallData]>;

llvm/lib/Target/Hexagon/HexagonSubtarget.cpp

HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
   // Beware of the default constructor of InstrItineraryData: it will
   // reset all members to 0.
   assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized");
 }
 
 HexagonSubtarget &
 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
   static std::map<StringRef, Hexagon::ArchEnum> CpuTable{
+      {"generic", Hexagon::ArchEnum::V60},
       {"hexagonv4", Hexagon::ArchEnum::V4},
       {"hexagonv5", Hexagon::ArchEnum::V5},
       {"hexagonv55", Hexagon::ArchEnum::V55},
       {"hexagonv60", Hexagon::ArchEnum::V60},
       {"hexagonv62", Hexagon::ArchEnum::V62},
       {"hexagonv65", Hexagon::ArchEnum::V65},
   };
 

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

std::string selectHexagonFS(StringRef CPU, StringRef FS) {
   return join(Result.begin(), Result.end(), ",");
 }
 }
 
 static bool isCPUValid(std::string CPU)
 {
   std::vector<std::string> table
   {
+    "generic",
     "hexagonv4",
     "hexagonv5",
     "hexagonv55",
     "hexagonv60",
     "hexagonv62",
     "hexagonv65",
   };
 

llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp

 using namespace llvm;
 
 Target &llvm::getTheHexagonTarget() {
   static Target TheHexagonTarget;
   return TheHexagonTarget;
 }
 
 extern "C" void LLVMInitializeHexagonTargetInfo() {
-  RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(
+  RegisterTarget<Triple::hexagon, /*HasJIT=*/true> X(
       getTheHexagonTarget(), "hexagon", "Hexagon", "Hexagon");
 }

llvm/test/CodeGen/Hexagon/generic-cpu.ll

+; RUN: llc -mtriple=hexagon-unknown-elf -mcpu=generic < %s | FileCheck %s
+
+; CHECK-NOT: invalid CPU
+
+define i32 @test(i32 %a) {
+  ret i32 0
+}