Add sign/zero extend to mips fast-isel

[rkotler]

Summary

Add sign/zero extend to mips fast-isel
(Rewrite of D3984)

[dsanders]

Seeing as you're starting a new review. Could you mark D3984 abandoned?

lib/Target/Mips/MipsFastISel.cpp

253–265

I think we could better write this as something like:

unsigned SizeInBits = SrcVT.getSizeInBits();
if (SizeInBits > GPRWidthInBits)
  return false;
if (SizeInBits == 8 && isMips32r2()) {
  EmitInst(Mips::SEB, DestReg).addReg(SrcReg);
  return true;
}
if (SizeInBits == 16 && isMips32r2()) {
  EmitInst(Mips::SEH, DestReg).addReg(SrcReg);
  return true;
}
EmitInst(Mips::SLL, DestReg).addReg(SrcReg).addImm(GPRWidth - SizeInBits); 
EmitInst(Mips::SRA, DestReg).addReg(DestReg).addImm(GPRWidth - SizeInBits);
return true;

rather than listing each case. This looks a bit longer but it handles MIPS32r1/MIPS64r2 (and earlier), as well as unusual types such as i11 using the SLL/SRA. Meanwhile, it still provides the faster output when SEB/SEH are available.

(I realize I'm violating SSA form in the last three lines of the example but it's just for explanation and should be easy to fix)

270–282

I think we could simplify this to something like:

if (SrcVT.getSizeInBits() <= 16)
  unsigned Mask = APInt::getMaxValue(SrcVT.getSizeInBits()).getZExtValue();
  EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Mask);
  return true;
}
return false;

rather than listing each case. It handles unusual types like i9 too.

390–393

Given that trunc is only valid for integers and vectors of integers, do we need to test the type combinations?

I think this this will suffice:

if (SrcVT.isVector() || DestVT.isVector())
  return false;

possibly with a check that the size in bits is <= 32

test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll

2

It would be preferable to write the testcase manually rather than use the output of clang. Clang's output tends to be overly complex and noisy for the kind of tests we need here.

For example:

@b1 = global i8 1, align 1
@i = global i32 0, align 4
define void @sext_i8_to_i16()  {
entry:
  %0 = load i8* @b1, align 1
  %1 = sext i8 %0 to i16
  store i16 %1, i32* @i, align 4
  ret void
}

25

Use CHECK-LABEL so that FileCheck divides the file into independent sections. Likewise for the other function labels below.

[rkotler]

• d4007
• Merge branch 'master' into reed-bug-04
• Merge branch 'master' into reed-bug-04

[rkotler]

I don't think that any of the proposed changes to my patch are necessary and I don't really agree with them helping the code and to the contrary I think they just make it more complicated and relying on things that may not always be true even, in the future.

Regarding not using the output of clang; this is something i can look into but i'm more comfortable at this time doing it the way I'm doing it and would have to get better at writing LLVM IR by hand.

I would like to submit the patch as is and we can revisit some of this later after the basic Mips fast-isel port is done. A lot of this will change anyway by then and certainly when we add mips64 which is not that far off.

[mcrosier]

In D4827#12, @rkotler wrote:

I don't think that any of the proposed changes to my patch are necessary and I don't really agree with them helping the code and to the contrary I think they just make it more complicated and relying on things that may not always be true even, in the future.

I very much agree with Reid.

Regarding not using the output of clang; this is something i can look into but i'm more comfortable at this time doing it the way I'm doing it and would have to get better at writing LLVM IR by hand.

I don't think this is a serious blocker.

I would like to submit the patch as is and we can revisit some of this later after the basic Mips fast-isel port is done. A lot of this will change anyway by then and certainly when we add mips64 which is not that far off.

I'm not giving the LGTM as I haven't closely followed the patch, but I am backing Reid's comments about the code refactoring being unnecessary and in fact harmful.

Chad

[mcrosier]

lib/Target/Mips/MipsFastISel.cpp

251

Consider refactoring EmitIntSExt into a single function with a bool parameter, isSigned, that indicates if we're sign-extending or zero-extending. I think as you continue to developer fast-isel you'll see a lot of redundancies between these functions.

357

clang-format?

Comments should be complete sentences with proper punctuation.

392

Pass isZExt as a parameter, per the suggestion above. Logic will be simplified here as well.

411

These are the correct type of checks, IMO. It is much easier to understand when reviewing/refactoring.

[dsanders]

In D4827#14, @mcrosier wrote:

In D4827#12, @rkotler wrote:

I don't think that any of the proposed changes to my patch are necessary and I don't really agree with them helping the code and to the contrary I think they just make it more complicated and relying on things that may not always be true even, in the future.

I very much agree with Reid.

I disagree but to a greater or lesser extent according to the change. I'll reply to each one inline with the reason for the request but the overarching principle is that I'd prefer to not to leave gaps in the implementation that need rediscovering at a later point since this has been a major source of pain in both the integrated assembler and code generator. The use of SEB/SEH (which requires MIPS32r2/MIPS64r2) without handling MIPS32r1/MIPS64r1 and earlier is a good example of this.

Regarding not using the output of clang; this is something i can look into but i'm more comfortable at this time doing it the way I'm doing it and would have to get better at writing LLVM IR by hand.

I don't think this is a serious blocker.

Indeed, it's not a serious blocker for an individual patch. I brought it up because I'd prefer that our test cases omit the unnecessary artifacts that clang introduces for its own convenience.

lib/Target/Mips/MipsFastISel.cpp

253–265

The intention of this request is for correctness for multiple ISA's. The code in the original patch is using instructions that only exist on MIPS32r2/MIPS64r2 and above. The request is to support all known MIPS ISA's with a trivial change by falling back on an SHL/SRA sequence.

270–282

This one is refactoring. A 16-bit immediate and instruction is available on all MIPS ISA's and it seemed strange to special case three particular sizes when a single calculation would do the same job.

390–393

This one is a query. It looked like the suggested code was equivalent and would remain so in the future. However, I couldn't be certain.

[rkotler]

This initial port is just mips32/r2, pic, O2 . I've added O0 as a requirement. Nothing else is part of what we are doing at this time.

Worrying about other combinations is for future work. Its out of scope at this time, IMO.

SOme of these things, had I know about them, might have made sense for me to do in this first go around but I've already done it this way and this is in the scope of the work and passes all of test-suite so I don't feel there is any need to be making more changes, do the testing, etc. to cases that are out of scope of my assigned work.

[mcrosier]

In D4827#16, @dsanders wrote:

In D4827#14, @mcrosier wrote:

In D4827#12, @rkotler wrote:

I don't think that any of the proposed changes to my patch are necessary and I don't really agree with them helping the code and to the contrary I think they just make it more complicated and relying on things that may not always be true even, in the future.

I very much agree with Reid.

And now I recant my statement. That's what I get for doing a drive-by review. Thank you for the clarification, Daniel.

I disagree but to a greater or lesser extent according to the change. I'll reply to each one inline with the reason for the request but the overarching principle is that I'd prefer to not to leave gaps in the implementation that need rediscovering at a later point since this has been a major source of pain in both the integrated assembler and code generator. The use of SEB/SEH (which requires MIPS32r2/MIPS64r2) without handling MIPS32r1/MIPS64r1 and earlier is a good example of this.

I didn't realized you were trying to support multiple implementations of the ISA. With that understanding, I'll now back Daniel (strongly). The implementation is incomplete.

Regarding not using the output of clang; this is something i can look into but i'm more comfortable at this time doing it the way I'm doing it and would have to get better at writing LLVM IR by hand.

I don't think this is a serious blocker.

Indeed, it's not a serious blocker for an individual patch. I brought it up because I'd prefer that our test cases omit the unnecessary artifacts that clang introduces for its own convenience.

Very understandable.

[rkotler]

What I meant regarding things that might have made sense would be to account for Mips R1 but I really don't see why.

[rkotler]

There are lots of Mips target and ABI variations. The scope of my work at this time is just Mips 32/r2, pic, o32 abi.

Everything else is out of scope.

What is in scope is to finish the whole piece of work for this configuration.

Redoing things that are not part of this scope of work slows down the whole project and is definitely contrary to getting the initial work done.

[rkotler]

In the constructor for mips fast isel is the following line of code:

TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
                   (Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));

If TargetSupported is false then we don't do Mips fast isel, even if it is requested.

[rkotler]

There is no reason to be concerned with mips32/r1 which is an old processor version as far as I know. We don't even have any build bots at Mips that test if we can pass test-suite with mips32/r1 as the processor as far as I know . If need a special sequence for mips32/r1, then I think it should be on an if statement of some kind rather that use a more obscure sequence that happens to to work on both mips32/r2 and mips32/r1. I used the most clear sequence for mips32/r2 which is our first target for mips fast-isel.

[dsanders]

In D4827#18, @mcrosier wrote:

In D4827#16, @dsanders wrote:

And now I recant my statement. That's what I get for doing a drive-by review. Thank you for the clarification, Daniel.

I disagree but to a greater or lesser extent according to the change. I'll reply to each one inline with the reason for the request but the overarching principle is that I'd prefer to not to leave gaps in the implementation that need rediscovering at a later point since this has been a major source of pain in both the integrated assembler and code generator. The use of SEB/SEH (which requires MIPS32r2/MIPS64r2) without handling MIPS32r1/MIPS64r1 and earlier is a good example of this.

I didn't realized you were trying to support multiple implementations of the ISA. With that understanding, I'll now back Daniel (strongly). The implementation is incomplete.

In the long run, yes. Reed is correct that his current work is focused on MIPS32r2 but I also need to look at the long term for the MIPS backend. It has proven difficult to add MIPS1-MIPS5 support on the SelectionDAG side of things because we jumped in at MIPS32r1 and ignored everything that came before and I'd like to avoid repeating the same mistake to a greater degree here. (As an aside, one of my colleagues is working towards fixing some of the MIPS1-MIPS5 issues in the tablegen definitions at the moment).

For easy things such as this case, it seems like an simple call to request the whole implementation. For more difficult things, I'll probably settle for appropriate if-statements and a FIXME comment so we can at least find it again easily.

In D4827#22, @rkotler wrote:

There is no reason to be concerned with mips32/r1 which is an old processor version as far as I know. We don't even have any build bots at Mips that test if we can pass test-suite with mips32/r1 as the processor as far as I know.

We still support MIPS32r1 and we are taking steps to support even earlier processors for various reasons. I'm testing MIPS32r1 as part of the LLVM 3.5 release and it fully passes. It's probably true that there are currently no MIPS32r1 builders at the moment but this is a reflection of lack of facilities rather than lack of need. This is something we're sorting out (along with much more) in the near future.

If need a special sequence for mips32/r1, then I think it should be on an if statement of some kind rather that use a more obscure sequence that happens to to work on both mips32/r2 and mips32/r1. I used the most clear sequence for mips32/r2 which is our first target for mips fast-isel.

Shift-left-shift-right isn't very obscure but more importantly the suggested code continues to use SEB/SEH when they are available so I'm not sure what you are getting at here.

In D4827#21, @rkotler wrote:

In the constructor for mips fast isel is the following line of code:

TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
                   (Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));

If TargetSupported is false then we don't do Mips fast isel, even if it is requested.

Indeed, this global check reduces the number of configurations you need to test straightaway and I'm ok with it as a way to manage the scale of the early testing. I still have reservations about this check leading to the omission of the local checks in the appropriate places though. If we're doing things correctly then we should be able to delete this check without affecting the correctness of FastISel..

[rkotler]

The statement

TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
                 (Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));

is there because that is the scope of the work I have been assigned by management to do for fast-isel.
There are important customers that need exactly that and nothing more.

It's not there to reduce the testing matrix.

The scope of the work is not to worry about doing fast-isel for other old or new Mips targets or abis.

We may never want to support fast-isel for old targets. That's a decision for management to make as far as fast-isel.
Just because we support old targets in some tools does not mean that it's to be supported uniformly for all new work on llvm, like for fast-isel.

RIght now they just want was is covered by the TargetSupported list.

After that I think the plan is to add 64 bit support.

I don't see how it's difficult to add others in later.

I'm digging my heels in a bit on this patch because I think these kinds of change requests are impeding the task at hand and I'd like
to hopefully rein in the scope here and not have to revisit this issue on every patch; what other things that are beyond the scope of my work assignment
I now to need to take into account and add to my patches.

There are about 10 patches in my queue right now which when submitted will take this first cut at mips fast-isel to a high percentage of completion.

lib/Target/Mips/MipsFastISel.cpp

 private:
   bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
                 unsigned Alignment = 0);
   bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
                  unsigned Alignment = 0);
   bool SelectLoad(const Instruction *I);
   bool SelectRet(const Instruction *I);
   bool SelectStore(const Instruction *I);
+  bool SelectIntExt(const Instruction *I);
+  bool SelectTrunc(const Instruction *I);
+  bool SelectFPExt(const Instruction *I);
 
   bool isTypeLegal(Type *Ty, MVT &VT);
   bool isLoadTypeLegal(Type *Ty, MVT &VT);
 
   unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
   unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
   unsigned MaterializeInt(const Constant *C, MVT VT);
   unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
 
+  bool EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
+
+  bool EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
+
   // for some reason, this default is not generated by tablegen
   // so we explicitly generate it here.
   //
   unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
                              unsigned Op0, bool Op0IsKill, uint64_t imm1,
                              uint64_t imm2, unsigned Op3, bool Op3IsKill) {
     return 0;
   }
case MVT::f64:
     break;
   default:
     return false;
   }
   EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
   return true;
 }
 
+bool MipsFastISel::EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
+                               unsigned DestReg) {
+  if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
+    return false;
+  switch (SrcVT.SimpleTy) {
+  default:
+    return false;
+  case MVT::i8:
+    EmitInst(Mips::SEB, DestReg).addReg(SrcReg);
+    break;
+  case MVT::i16:
+    EmitInst(Mips::SEH, DestReg).addReg(SrcReg);
+    break;
+  }
+  return true;
+}
+
+bool MipsFastISel::EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
+                               unsigned DestReg) {
+  switch (SrcVT.SimpleTy) {
+  default:
+    return false;
+  case MVT::i1:
+    EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
+    break;
+  case MVT::i8:
+    EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
+    break;
+  case MVT::i16:
+    EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
+    break;
+  }
+  return true;
+}
+
 bool MipsFastISel::SelectLoad(const Instruction *I) {
   // Atomic loads need special handling.
   if (cast<LoadInst>(I)->isAtomic())
     return false;
 
   // Verify we have a legal type before going any further.
   MVT VT;
   if (!isLoadTypeLegal(I->getType(), VT))
if (!FuncInfo.CanLowerReturn)
     return false;
   if (Ret->getNumOperands() > 0) {
     return false;
   }
   EmitInst(Mips::RetRA);
   return true;
 }
 
+// Attempt to fast-select a floating-point extend instruction.
+bool MipsFastISel::SelectFPExt(const Instruction *I) {
+  Value *Src = I->getOperand(0);
+  EVT SrcVT = TLI.getValueType(Src->getType(), true);
+  EVT DestVT = TLI.getValueType(I->getType(), true);
+
+  if (SrcVT != MVT::f32 || DestVT != MVT::f64)
+    return false;
+
+  unsigned SrcReg =
+      getRegForValue(Src); // his must be a 32 bit floating point register class
+                           // maybe we should handle this differently
+  if (!SrcReg)
+    return false;
+
+  unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
+  EmitInst(Mips::CVT_D_S_MM, DestReg).addReg(SrcReg);
+  UpdateValueMap(I, DestReg);
+  return true;
+}
+
+bool MipsFastISel::SelectIntExt(const Instruction *I) {
+  Type *DestTy = I->getType();
+  Value *Src = I->getOperand(0);
+  Type *SrcTy = Src->getType();
+
+  bool isZExt = isa<ZExtInst>(I);
+  unsigned SrcReg = getRegForValue(Src);
+  if (!SrcReg)
+    return false;
+
+  EVT SrcEVT, DestEVT;
+  SrcEVT = TLI.getValueType(SrcTy, true);
+  DestEVT = TLI.getValueType(DestTy, true);
+  if (!SrcEVT.isSimple())
+    return false;
+  if (!DestEVT.isSimple())
+    return false;
+
+  MVT SrcVT = SrcEVT.getSimpleVT();
+  MVT DestVT = DestEVT.getSimpleVT();
+  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
+
+  if (isZExt) {
+    if (!EmitIntZExt(SrcVT, SrcReg, DestVT, ResultReg))
+      return false;
+  } else {
+    if (!EmitIntSExt(SrcVT, SrcReg, DestVT, ResultReg))
+      return false;
+  }
+  UpdateValueMap(I, ResultReg);
+  return true;
+}
+
+bool MipsFastISel::SelectTrunc(const Instruction *I) {
+  // The high bits for a type smaller than the register size are assumed to be
+  // undefined.
+  Value *Op = I->getOperand(0);
+
+  EVT SrcVT, DestVT;
+  SrcVT = TLI.getValueType(Op->getType(), true);
+  DestVT = TLI.getValueType(I->getType(), true);
+
+  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
+    return false;
+  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
+    return false;
+
+  unsigned SrcReg = getRegForValue(Op);
+  if (!SrcReg)
+    return false;
+
+  // Because the high bits are undefined, a truncate doesn't generate
+  // any code.
+  UpdateValueMap(I, SrcReg);
+  return true;
+}
+
 bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
   if (!TargetSupported)
     return false;
   switch (I->getOpcode()) {
   default:
     break;
   case Instruction::Load:
     return SelectLoad(I);
   case Instruction::Store:
     return SelectStore(I);
   case Instruction::Ret:
     return SelectRet(I);
+  case Instruction::Trunc:
+    return SelectTrunc(I);
+  case Instruction::ZExt:
+  case Instruction::SExt:
+    return SelectIntExt(I);
+  case Instruction::FPExt:
+    return SelectFPExt(I);
   }
   return false;
 }
 }
 
 unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
   int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
   if (VT == MVT::f32) {

test/CodeGen/Mips/Fast-ISel/fpext.ll

+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s
+
+@f = global float 0x40147E6B80000000, align 4
+@d_f = common global double 0.000000e+00, align 8
+@.str = private unnamed_addr constant [6 x i8] c"%f  \0A\00", align 1
+
+; Function Attrs: nounwind
+define void @dv() #0 {
+entry:
+  %0 = load float* @f, align 4
+  %conv = fpext float %0 to double
+; CHECK: cvt.d.s  $f{{[0-9]+}}, $f{{[0-9]+}}
+  store double %conv, double* @d_f, align 8
+  ret void
+}
+
+
+attributes #1 = { nounwind }

test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll

+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s
+
+@b2 = global i8 0, align 1
+@b1 = global i8 1, align 1
+@uc1 = global i8 0, align 1
+@uc2 = global i8 -1, align 1
+@sc1 = global i8 -128, align 1
+@sc2 = global i8 127, align 1
+@ss1 = global i16 -32768, align 2
+@ss2 = global i16 32767, align 2
+@us1 = global i16 0, align 2
+@us2 = global i16 -1, align 2
+@ssi = global i16 0, align 2
+@ssj = global i16 0, align 2
+@i = global i32 0, align 4
+@j = global i32 0, align 4
+@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1
+@.str1 = private unnamed_addr constant [7 x i8] c"%i %i\0A\00", align 1
+
+; Function Attrs: nounwind
+define void @_Z3b_iv() #0 {
+entry:
+; CHECK:   .ent  _Z3b_iv
+  %0 = load i8* @b1, align 1
+  %tobool = trunc i8 %0 to i1
+  %frombool = zext i1 %tobool to i8
+  store i8 %frombool, i8* @b2, align 1
+  %1 = load i8* @b2, align 1
+  %tobool1 = trunc i8 %1 to i1
+  %conv = zext i1 %tobool1 to i32
+  store i32 %conv, i32* @i, align 4
+; CHECK:  lbu  ${{[0-9]+}}, 0(${{[0-9]+}})
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 1
+; CHECK:  sb  ${{[0-9]+}}, 0(${{[0-9]+}})
+
+
+
+  ret void
+; CHECK:   .end  _Z3b_iv
+}
+
+; Function Attrs: nounwind
+define void @_Z4uc_iv() #0 {
+entry:
+; CHECK:  .ent  _Z4uc_iv
+
+  %0 = load i8* @uc1, align 1
+  %conv = zext i8 %0 to i32
+  store i32 %conv, i32* @i, align 4
+  %1 = load i8* @uc2, align 1
+  %conv1 = zext i8 %1 to i32
+; CHECK:   lbu  ${{[0-9]+}}, 0(${{[0-9]+}})
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 255
+
+  store i32 %conv1, i32* @j, align 4
+  ret void
+; CHECK:  .end  _Z4uc_iv
+
+}
+
+; Function Attrs: nounwind
+define void @_Z4sc_iv() #0 {
+entry:
+; CHECK:  .ent  _Z4sc_iv
+
+  %0 = load i8* @sc1, align 1
+  %conv = sext i8 %0 to i32
+  store i32 %conv, i32* @i, align 4
+  %1 = load i8* @sc2, align 1
+  %conv1 = sext i8 %1 to i32
+  store i32 %conv1, i32* @j, align 4
+; CHECK:  lbu  ${{[0-9]+}}, 0(${{[0-9]+}})
+; CHECK:  seb  ${{[0-9]+}}, ${{[0-9]+}}
+
+  ret void
+; CHECK:  .end  _Z4sc_iv
+}
+
+; Function Attrs: nounwind
+define void @_Z4us_iv() #0 {
+entry:
+; CHECK:  .ent  _Z4us_iv
+  %0 = load i16* @us1, align 2
+  %conv = zext i16 %0 to i32
+  store i32 %conv, i32* @i, align 4
+  %1 = load i16* @us2, align 2
+  %conv1 = zext i16 %1 to i32
+  store i32 %conv1, i32* @j, align 4
+  ret void
+; CHECK:  lhu  ${{[0-9]+}}, 0(${{[0-9]+}})
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 65535
+; CHECK:  .end  _Z4us_iv
+}
+
+; Function Attrs: nounwind
+define void @_Z4ss_iv() #0 {
+entry:
+; CHECK:  .ent  _Z4ss_iv
+
+  %0 = load i16* @ss1, align 2
+  %conv = sext i16 %0 to i32
+  store i32 %conv, i32* @i, align 4
+  %1 = load i16* @ss2, align 2
+  %conv1 = sext i16 %1 to i32
+  store i32 %conv1, i32* @j, align 4
+; CHECK:   lhu  ${{[0-9]+}}, 0(${{[0-9]+}})
+; CHECK:  seh  ${{[0-9]+}}, ${{[0-9]+}}
+
+  ret void
+; CHECK:  .end  _Z4ss_iv
+}
+
+; Function Attrs: nounwind
+define void @_Z4b_ssv() #0 {
+entry:
+; CHECK:  .ent  _Z4b_ssv
+  %0 = load i8* @b2, align 1
+  %tobool = trunc i8 %0 to i1
+  %conv = zext i1 %tobool to i16
+  store i16 %conv, i16* @ssi, align 2
+  ret void
+; CHECK:  lbu  ${{[0-9]+}}, 0(${{[0-9]+}})
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 1
+; CHECK:  .end  _Z4b_ssv
+}
+
+; Function Attrs: nounwind
+define void @_Z5uc_ssv() #0 {
+entry:
+; CHECK:  .ent  _Z5uc_ssv
+  %0 = load i8* @uc1, align 1
+  %conv = zext i8 %0 to i16
+  store i16 %conv, i16* @ssi, align 2
+  %1 = load i8* @uc2, align 1
+  %conv1 = zext i8 %1 to i16
+; CHECK:   lbu  ${{[0-9]+}}, 0(${{[0-9]+}})
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 255
+
+  store i16 %conv1, i16* @ssj, align 2
+  ret void
+; CHECK:  .end  _Z5uc_ssv
+}
+
+; Function Attrs: nounwind
+define void @_Z5sc_ssv() #0 {
+entry:
+; CHECK:  .ent  _Z5sc_ssv
+  %0 = load i8* @sc1, align 1
+  %conv = sext i8 %0 to i16
+  store i16 %conv, i16* @ssi, align 2
+  %1 = load i8* @sc2, align 1
+  %conv1 = sext i8 %1 to i16
+  store i16 %conv1, i16* @ssj, align 2
+; CHECK:  lbu  ${{[0-9]+}}, 0(${{[0-9]+}})
+; CHECK:  seb  ${{[0-9]+}}, ${{[0-9]+}}
+
+  ret void
+; CHECK:  .end  _Z5sc_ssv
+}
+
+declare i32 @printf(i8*, ...) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }