[AArch64] Added support for the vcvta_u16_f16 instrinsic for FP16 Armv8.2-A

[LukeGeeson]

Summary

-Added support for existing IP for vcvta_u16_f16 instrinsic for Armv8.2A
-CGBuiltin simply adds cases for this intrinsic to gen the clang IR
-tests added for AArch64 and Arm test suites
-tested and works using ninja check

[SjoerdMeijer]

Nits title:

• Think you can simplify the title to something along the lines of: "[AArch64] Support the FP16 VCVTA_U16 intrinsic". No need to mention tests are added in the subject (tests should always be added).

Nits summary:

• Arm v8.2a -> Armv8.2-A
• Aarch64 -> AArch64
• No need to mention "tested and works using ninja check"; this is obvious and should always be done.
• This is a bit vague: "Added support for existing IP". I think you can reduce the summary to just: "Added support for the vcvta_u16_f16 instrinsic for FP16 Armv8.2-A"

CodeGen/arm-v8.2a-neon-intrinsics.c

170

Is this exactly the same test also added in aarch64-v8.2a-neon-intrinsics.c?

[LukeGeeson]

address Nit's and code comments, please see above.

CodeGen/arm-v8.2a-neon-intrinsics.c

170

Not that I'm aware. One is for AArch platforms and the other is Arm. see the second CHECK line of each

[SjoerdMeijer]

Thanks. Looks like a straightforward fix to me.

CodeGen/arm-v8.2a-neon-intrinsics.c

170

Ah, of course, my bad. Looked too quickly.

CodeGen/CGBuiltin.cpp

   NEONMAP1(vcvt_n_u64_v, arm_neon_vcvtfp2fxu, 0),
   NEONMAP0(vcvt_s16_v),
   NEONMAP0(vcvt_s32_v),
   NEONMAP0(vcvt_s64_v),
   NEONMAP0(vcvt_u16_v),
   NEONMAP0(vcvt_u32_v),
   NEONMAP0(vcvt_u64_v),
   NEONMAP1(vcvta_s16_v, arm_neon_vcvtas, 0),
+  NEONMAP1(vcvta_u16_v, arm_neon_vcvtau, 0),
   NEONMAP1(vcvta_s32_v, arm_neon_vcvtas, 0),
   NEONMAP1(vcvta_s64_v, arm_neon_vcvtas, 0),
   NEONMAP1(vcvta_u32_v, arm_neon_vcvtau, 0),
   NEONMAP1(vcvta_u64_v, arm_neon_vcvtau, 0),
   NEONMAP1(vcvtaq_s16_v, arm_neon_vcvtas, 0),
   NEONMAP1(vcvtaq_s32_v, arm_neon_vcvtas, 0),
   NEONMAP1(vcvtaq_s64_v, arm_neon_vcvtas, 0),
   NEONMAP1(vcvtaq_u16_v, arm_neon_vcvtau, 0),

   case NEON::BI__builtin_neon_vcvtq_u64_v:
   case NEON::BI__builtin_neon_vcvtq_s16_v:
   case NEON::BI__builtin_neon_vcvtq_u16_v: {
     Ops[0] = Builder.CreateBitCast(Ops[0], GetFloatNeonType(this, Type));
     return Usgn ? Builder.CreateFPToUI(Ops[0], Ty, "vcvt")
                 : Builder.CreateFPToSI(Ops[0], Ty, "vcvt");
   }
   case NEON::BI__builtin_neon_vcvta_s16_v:
+  case NEON::BI__builtin_neon_vcvta_u16_v:
   case NEON::BI__builtin_neon_vcvta_s32_v:
   case NEON::BI__builtin_neon_vcvta_s64_v:
   case NEON::BI__builtin_neon_vcvta_u32_v:
   case NEON::BI__builtin_neon_vcvta_u64_v:
   case NEON::BI__builtin_neon_vcvtaq_s16_v:
   case NEON::BI__builtin_neon_vcvtaq_s32_v:
   case NEON::BI__builtin_neon_vcvtaq_s64_v:
   case NEON::BI__builtin_neon_vcvtaq_u16_v:

   case NEON::BI__builtin_neon_vcvtq_s16_v:
   case NEON::BI__builtin_neon_vcvtq_u16_v: {
     Ops[0] = Builder.CreateBitCast(Ops[0], GetFloatNeonType(this, Type));
     if (usgn)
       return Builder.CreateFPToUI(Ops[0], Ty);
     return Builder.CreateFPToSI(Ops[0], Ty);
   }
   case NEON::BI__builtin_neon_vcvta_s16_v:
+  case NEON::BI__builtin_neon_vcvta_u16_v:
   case NEON::BI__builtin_neon_vcvta_s32_v:
   case NEON::BI__builtin_neon_vcvtaq_s16_v:
   case NEON::BI__builtin_neon_vcvtaq_s32_v:
   case NEON::BI__builtin_neon_vcvta_u32_v:
   case NEON::BI__builtin_neon_vcvtaq_u16_v:
   case NEON::BI__builtin_neon_vcvtaq_u32_v:
   case NEON::BI__builtin_neon_vcvta_s64_v:
   case NEON::BI__builtin_neon_vcvtaq_s64_v:

CodeGen/aarch64-v8.2a-neon-intrinsics.c

 
 // CHECK-LABEL: test_vcvta_s16_f16
 // CHECK:  [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtas.v4i16.v4f16(<4 x half> %a)
 // CHECK:  ret <4 x i16> [[VCVT]]
 int16x4_t test_vcvta_s16_f16 (float16x4_t a) {
   return vcvta_s16_f16(a);
 }
 
+// CHECK-LABEL: test_vcvta_u16_f16
+// CHECK:  [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtau.v4i16.v4f16(<4 x half> %a)
+// CHECK:  ret <4 x i16> [[VCVT]]
+int16x4_t test_vcvta_u16_f16 (float16x4_t a) {
+  return vcvta_u16_f16(a);
+}
+
 // CHECK-LABEL: test_vcvtaq_s16_f16
 // CHECK:  [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtas.v8i16.v8f16(<8 x half> %a)
 // CHECK:  ret <8 x i16> [[VCVT]]
 int16x8_t test_vcvtaq_s16_f16 (float16x8_t a) {
   return vcvtaq_s16_f16(a);
 }
 
 // CHECK-LABEL: test_vcvtm_s16_f16

CodeGen/arm-v8.2a-neon-intrinsics.c

 
 // CHECK-LABEL: test_vcvta_s16_f16
 // CHECK:  [[VCVT:%.*]] = call <4 x i16> @llvm.arm.neon.vcvtas.v4i16.v4f16(<4 x half> %a)
 // CHECK:  ret <4 x i16> [[VCVT]]
 int16x4_t test_vcvta_s16_f16 (float16x4_t a) {
   return vcvta_s16_f16(a);
 }
 
+// CHECK-LABEL: test_vcvta_u16_f16
+// CHECK:  [[VCVT:%.*]] = call <4 x i16> @llvm.arm.neon.fcvtau.v4i16.v4f16(<4 x half> %a)
+// CHECK:  ret <4 x i16> [[VCVT]]
+int16x4_t test_vcvta_u16_f16 (float16x4_t a) {
+   return vcvta_u16_f16(a);
+}
+
 // CHECK-LABEL: test_vcvtaq_s16_f16
 // CHECK:  [[VCVT:%.*]] = call <8 x i16> @llvm.arm.neon.vcvtas.v8i16.v8f16(<8 x half> %a)
 // CHECK:  ret <8 x i16> [[VCVT]]
 int16x8_t test_vcvtaq_s16_f16 (float16x8_t a) {
   return vcvtaq_s16_f16(a);
 }
 
 // CHECK-LABEL: test_vcvtm_s16_f16