[MIRParser] Update a diagnostic message to use the correct register sigil. NFC

[mattd]

Summary

Patch r323922 changed the sigil for physical registers to '$', instead of '%'.
An error message was missed during this change, and reports the wrong sigil.
This patch corrects that diagnostic and the tests that check that error string.

[plotfi]

I did the sigil change and now I'm curious why I hadn't hit this a few months back. Do you know why?

[mattd]

It looks like you simply missed the diagnostic, and not any functional part. I only discovered it because I was messing around with a .mir test and noticed the error message. I'm guessing your search/replace didn't cover the case of an isolated '$'

[mattd]

Ping. Just checking back in to make sure that this patch makes sense.

[bjope]

LGTM!

[mattd]

Thanks for the review @bjope!

llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp

bool MIParser::verifyImplicitOperands(ArrayRef<ParsedMachineOperand> Operands,
 
   const auto *TRI = MF.getSubtarget().getRegisterInfo();
   assert(TRI && "Expected target register info");
   for (const auto &I : ImplicitOperands) {
     if (isImplicitOperandIn(I, Operands))
       continue;
     return error(Operands.empty() ? Token.location() : Operands.back().End,
                  Twine("missing implicit register operand '") +
-                     printImplicitRegisterFlag(I) + " %" +
+                     printImplicitRegisterFlag(I) + " $" +
                      getRegisterName(TRI, I.getReg()) + "'");
   }
   return false;
 }
 
 bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
   // Allow frame and fast math flags for OPCODE
   while (Token.is(MIToken::kw_frame_setup) ||

llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir

 
 ...
 ---
 name:            foo
 body: |
   bb.0.entry:
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-  ; CHECK: [[@LINE+1]]:35: missing implicit register operand 'implicit %eflags'
+  ; CHECK: [[@LINE+1]]:35: missing implicit register operand 'implicit $eflags'
     JG_1 %bb.2.exit, implicit $eax
 
   bb.1.less:
     $eax = MOV32r0 implicit-def $eflags
 
   bb.2.exit:
     RETQ $eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir

 
 ...
 ---
 name:            foo
 body: |
   bb.0.entry:
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-  ; CHECK: [[@LINE+1]]:42: missing implicit register operand 'implicit %eflags'
+  ; CHECK: [[@LINE+1]]:42: missing implicit register operand 'implicit $eflags'
     JG_1 %bb.2.exit, implicit-def $eflags
 
   bb.1.less:
     $eax = MOV32r0 implicit-def $eflags
 
   bb.2.exit:
     RETQ $eax
 ...

llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir

 ---
 name:            foo
 body: |
   bb.0.entry:
     successors: %bb.1.less, %bb.2.exit
 
     $eax = MOV32rm $rdi, 1, _, 0, _
     CMP32ri8 $eax, 10, implicit-def $eflags
-  ; CHECK: [[@LINE+1]]:20: missing implicit register operand 'implicit %eflags'
+  ; CHECK: [[@LINE+1]]:20: missing implicit register operand 'implicit $eflags'
     JG_1 %bb.2.exit
 
   bb.1.less:
     $eax = MOV32r0 implicit-def $eflags
 
   bb.2.exit:
     RETQ $eax
 ...