[PowerPC] avoid unprofitable Repl32 flag in BitPermutationSelector

[inouehrs]

Summary

BitPermutationSelector sets Repl32 flag for bit groups which can be (potentially) benefit from 32-bit rotate-and-mask instructions with bit replication, i.e. rlwinm/rlwimi copies lower 32 bits into upper 32 bits on 64-bit PowerPC before rotation.
However, enforcing 32-bit instruction sometimes results in redundant generated code.
For example, the following simple code is compiled into rotldi + rlwimi while it can be compiled into only rldimi instruction if Repl32 flag is not set on the bit group for (a & 0xFFFFFFFF).

uint64_t func(uint64_t a, uint64_t b) {
	return (a & 0xFFFFFFFF) | (b << 32) ;
}

To avoid such problem, this patch checks the potential benefit of Repl32 flag before setting it. If a bit group does not require rotation (i.e. RLAmt == 0) and won't be merged into another group, we do not benefit from Repl32 flag on this group.

[hfinkel]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

1455 ↗

(On Diff #150255)

insrtruction -> instruction

1460 ↗

(On Diff #150255)

Don't you also need to check that the StartIdx or EndIdx is 0 or 32?

[inouehrs]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

1460 ↗

(On Diff #150255)

Based on this condition, I think merging can happen if StartIdx and EndIdx are not 0 or 32.

if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
    I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {

I want to be conservative for not to reduce the opportunity of using Repl32 flag.

[hfinkel]

LGTM

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

1460 ↗

(On Diff #150255)

Makes sense.

llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

auto IsAllLow32 = [this](BitGroup & BG) {
             return false;
         }
       }
 
       return true;
     };
 
     for (auto &BG : BitGroups) {
+      // If this bit group has RLAmt of 0 and will not be merged with
+      // another bit group, we don't benefit from Repl32. We don't mark
+      // such group to give more freedom for later instruction selection.
+      if (BG.RLAmt == 0) {
+        auto PotentiallyMerged = [this](BitGroup & BG) {
+          for (auto &BG2 : BitGroups)
+            if (&BG != &BG2 && BG.V == BG2.V &&
+                (BG2.RLAmt == 0 || BG2.RLAmt == 32))
+              return true;
+          return false;
+        };
+        if (!PotentiallyMerged(BG))
+          continue;
+      }
       if (BG.StartIdx < 32 && BG.EndIdx < 32) {
         if (IsAllLow32(BG)) {
           if (BG.RLAmt >= 32) {
             BG.RLAmt -= 32;
             BG.Repl32CR = true;
           }
 
           BG.Repl32 = true;

llvm/trunk/test/CodeGen/PowerPC/bperm.ll

entry:
   %or3 = or i64 %or, %and
   ret i64 %or3
 
 ; CHECK-LABEL: @test15
 ; CHECK: rlwimi 3, 3, 4, 24, 31
 ; CHECK: blr
 }
 
+define i64 @test16(i64 %a, i64 %b) #0 {
+entry:
+  %and = and i64 %a, 4294967295
+  %shl = shl i64 %b, 32
+  %or = or i64 %and, %shl
+  ret i64 %or
+
+; CHECK-LABEL: @test16
+; CHECK: rldimi 3, 4, 32, 0
+; CHECK: blr
+}
+
 ; Function Attrs: nounwind readnone
 declare i32 @llvm.bswap.i32(i32) #0
 declare i64 @llvm.bswap.i64(i64) #0
 
 attributes #0 = { nounwind readnone }