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[X86] Extract latency of fldz/fld1 in separate classes.
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Authored by courbet on May 30 2018, 2:36 AM.

Details

Summary
  • I've measured the values for Broadwell, Haswell, SandyBridge, Skylake.
  • For ZnVer1 and Atom, values were transferred form InstRWs.
  • For SLM and BtVer2, values are from Agner.

This is split off from https://reviews.llvm.org/D47377

Diff Detail

Repository
rL LLVM

Event Timeline

courbet created this revision.May 30 2018, 2:36 AM
RKSimon added inline comments.May 30 2018, 8:10 AM
lib/Target/X86/X86InstrFPStack.td
658 ↗(On Diff #149068)

Please pull these 5 FLD* entries out and classify as WriteFLDC (see X86Schedule.td)

lib/Target/X86/X86Schedule.td
146 ↗(On Diff #149068)

Shorten the names to WriteFLD0, WriteFLD1, - allows you to remove all the indentation changes.

Please add WriteFLDC for the other math constants (FLDPI etc.)

lib/Target/X86/X86ScheduleBtVer2.td
275 ↗(On Diff #149068)

Checked with the AMD16h SOG - these should be [JFPU1, JSTC], 3, [1,1,], 1

lib/Target/X86/X86ScheduleZnver1.td
818 ↗(On Diff #149068)

Just replace these with SchedAlias instead of entries above - that's what is mainly used in znver1

courbet updated this revision to Diff 149128.May 30 2018, 8:34 AM
courbet marked an inline comment as done.
  • Use WriteFLD0/1 instread of WriteF80Constant0/1.
  • Fix btver2 data as suggested by Simon.

Thanks

lib/Target/X86/X86Schedule.td
146 ↗(On Diff #149068)

Shorten the names to WriteFLD0, WriteFLD1, - allows you to remove all the indentation changes.

Done.

Please add WriteFLDC for the other math constants (FLDPI etc.)

If you don't mind I'll tacle this one in a separate diff.

lib/Target/X86/X86ScheduleZnver1.td
818 ↗(On Diff #149068)

I'm not sure what you mean.
Getting rid of the definition for ZnWriteFPU3 and alias it to WriteFLD0 ?

RKSimon added inline comments.May 30 2018, 8:46 AM
lib/Target/X86/X86ScheduleZnver1.td
818 ↗(On Diff #149068)

You can remove the X86WriteRes<WriteFLD* entries and update these existing entries here:

// FLDZ.
def : SchedAlias<WriteFLD0, ZnWriteFPU13>;

// FLD1.
def : SchedAlias<WriteFLD1, ZnWriteFPU3>;
courbet updated this revision to Diff 149234.May 30 2018, 11:13 PM

use SchedAliases on ZnVer1, update tests for BtVer2.

RKSimon accepted this revision.May 31 2018, 3:46 AM

LGTM with 2 minors

lib/Target/X86/X86InstrFPStack.td
569 ↗(On Diff #149234)

Drop the braces for single entries like this

lib/Target/X86/X86Schedule.td
146 ↗(On Diff #149068)

Really pedantic but please could you put these new entries above WriteFLoad so all the WriteFLoad* tags are together.

This revision is now accepted and ready to land.May 31 2018, 3:46 AM
courbet updated this revision to Diff 149262.May 31 2018, 4:37 AM
courbet marked an inline comment as done.

Address review comments.

Thanks for the review !

This revision was automatically updated to reflect the committed changes.