[Sparc] Select correct register class for FP register constraints

[dcederman]

Summary

The fX version of floating-point registers only supports single precision. We need to map the name to dX for doubles and qX for long doubles if we want getRegForInlineAsmConstraint() to be able to pick the correct register class.

[jyknight]

Some test cases for the error cases would be good here (e.g. "{f1}" with a double).

lib/Target/Sparc/SparcISelLowering.cpp

3501–3504

Ugh, unrelated to this commit, but this just made me notice that in Clang's inline asm code, we convert register names *to* r0-r31, only to convert it back, here. That's just silly.

3516

As a note, that SparcAsmParser.cpp has to do something very similar in MorphToDoubleReg. It might be nice if they could use the same code. But, this seems fine for now.

[dcederman]

Added tests for some error cases.

lib/Target/Sparc/SparcISelLowering.cpp

case 'e':
       break;
     }
   } else if (!Constraint.empty() && Constraint.size() <= 5
               && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
     // constraint = '{r<d>}'
     // Remove the braces from around the name.
     StringRef name(Constraint.data()+1, Constraint.size()-2);
     // Handle register aliases:
     //       r0-r7   -> g0-g7
     //       r8-r15  -> o0-o7
     //       r16-r23 -> l0-l7
     //       r24-r31 -> i0-i7
     uint64_t intVal = 0;
     if (name.substr(0, 1).equals("r")
         && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
       const char regTypes[] = { 'g', 'o', 'l', 'i' };
       char regType = regTypes[intVal/8];
       char regIdx = '0' + (intVal % 8);
       char tmp[] = { '{', regType, regIdx, '}', 0 };
       std::string newConstraint = std::string(tmp);
       return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint,
                                                           VT);
     }
+    if (name.substr(0, 1).equals("f") &&
+        !name.substr(1).getAsInteger(10, intVal) && intVal <= 63) {
+      std::string newConstraint;
+
+      if (VT == MVT::f32) {
+        newConstraint = "{f" + utostr(intVal) + "}";
+      } else if (VT == MVT::f64 && (intVal % 2 == 0)) {
+        newConstraint = "{d" + utostr(intVal / 2) + "}";
+      } else if (VT == MVT::f128 && (intVal % 4 == 0)) {
+        newConstraint = "{q" + utostr(intVal / 4) + "}";
+      } else {
+        return std::make_pair(0U, nullptr);
+      }
+      return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint,
+                                                          VT);
+    }
   }
 
   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 }
 
 bool
 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
   // The Sparc target isn't yet aware of offsets.

test/CodeGen/SPARC/inlineasm-v9.ll

 ; CHECK: fmovd  %f0, %f2
 ; CHECK: faddd  %f2, %f32, %f2
 define double @faddd_high(double, double) local_unnamed_addr #2 {
 entry:
   %2 = tail call double asm sideeffect "faddd  $1, $2, $0;", "=f,f,e,~{d0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7}"(double %0, double %1) #7
   ret double %2
 }
 
+; CHECK-LABEL: test_constraint_float_reg:
+; CHECK: fadds %f20, %f20, %f20
+; CHECK: faddd %f20, %f20, %f20
+; CHECK: faddq %f40, %f40, %f40
+define void @test_constraint_float_reg() {
+entry:
+  tail call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"(float 6.0, float 7.0, float 8.0)
+  tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, double 11.0)
+  tail call void asm sideeffect "faddq $0,$1,$2", "{f40},{f40},{f40}"(fp128 0xL0, fp128 0xL0, fp128 0xL0)
+  ret void
+}

test/CodeGen/SPARC/inlineasm.ll

 
 ; CHECK-LABEL: test_addressing_mode_i64:
 ; CHECK: std %l0, [%o0]
 define void @test_addressing_mode_i64(i64* %out) {
 entry:
   call void asm "std %l0, $0", "=*m,r"(i64* nonnull %out, i64 0)
   ret void
 }
+
+; CHECK-LABEL: test_constraint_float_reg:
+; CHECK: fadds %f20, %f20, %f20
+; CHECK: faddd %f20, %f20, %f20
+define void @test_constraint_float_reg() {
+entry:
+  tail call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"(float 6.0, float 7.0, float 8.0)
+  tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, double 11.0)
+  ret void
+}