[MachineOutliner] Don't outline instructions that modify SP.

[efriedma]

Summary

This breaks the code which saves and restores LR, so we can't outline without doing something more complicated for stack adjustment.

Found by inspection; we get lucky in most cases because getMemOpInfo only handles STRWpost, not any other pre/post-increment forms. But it hits a couple of artificial testcases in the tree.

[paquette]

Thanks for finding this! LGTM.

(Since instructions like add x0, sp, #8 are extremely common it would probably be good to catch them somehow. Could probably be done for MBBs without calls by just checking to see if a scratch register is available for the save/restore.)

lib/Target/AArch64/AArch64InstrInfo.cpp

if (MI.modifiesRegister(AArch64::SP, &RI) ||
     // If we mess with the stack to save something, then an ADDXri messes with
     // it *after*, then we aren't going to restore the right something from
     // the stack if we don't outline the corresponding SUBXri first. ADDXris and
     // SUBXris are extremely common in prologue/epilogue code, so supporting
     // them in the outliner can be a pretty big win!
     if (!MightNeedStackFixUp)
       return MachineOutlinerInstrType::Legal;
 
+    // Any modification of SP will break our code to save/restore LR.
+    // FIXME: We could handle some instructions which add a constant offset to
+    // SP, with a bit more work.
+    if (MI.modifiesRegister(AArch64::SP, &RI))
+      return MachineOutlinerInstrType::Illegal;
+
     // At this point, we have a stack instruction that we might need to fix
     // up. We'll handle it if it's a load or store.
     if (MI.mayLoadOrStore()) {
       unsigned Base;  // Filled with the base regiser of MI.
       int64_t Offset; // Filled with the offset of MI.
       unsigned DummyWidth;
 
       // Does it allow us to offset the base register and is the base SP?
if (MI.mayLoadOrStore()) {
       Offset += 16; // Update the offset to what it would be if we outlined.
       if (Offset < MinOffset * Scale || Offset > MaxOffset * Scale)
         return MachineOutlinerInstrType::Illegal;
 
       // It's in range, so we can outline it.
       return MachineOutlinerInstrType::Legal;
     }
 
+    // FIXME: Add handling for instructions like "add x0, sp, #8".
+
     // We can't fix it up, so don't outline it.
     return MachineOutlinerInstrType::Illegal;
   }
 
   return MachineOutlinerInstrType::Legal;
 }
 
 void AArch64InstrInfo::fixupPostOutline(MachineBasicBlock &MBB) const {

test/CodeGen/AArch64/machine-outliner-remarks.ll

 ; RUN: llc %s -enable-machine-outliner -mtriple=aarch64-unknown-unknown -pass-remarks=machine-outliner -pass-remarks-missed=machine-outliner -o /dev/null 2>&1 | FileCheck %s
 ; CHECK: machine-outliner-remarks.ll:5:9:
 ; CHECK-SAME: Did not outline 2 instructions from 2 locations.
 ; CHECK-SAME: Instructions from outlining all occurrences (9) >=
 ; CHECK-SAME: Unoutlined instruction count (4)
 ; CHECK-SAME: (Also found at: machine-outliner-remarks.ll:13:9)
-; CHECK: remark: <unknown>:0:0: Saved 5 instructions by outlining 7 instructions
-; CHECK-SAME: from 2 locations. (Found at: machine-outliner-remarks.ll:27:9,
-; CHECK-SAME: machine-outliner-remarks.ll:36:1)
+; CHECK: remark: <unknown>:0:0: Saved 5 instructions by outlining 12 instructions
+; CHECK-SAME: from 2 locations. (Found at: machine-outliner-remarks.ll:36:1,
+; CHECK-SAME: machine-outliner-remarks.ll:27:9)
 ; RUN: llc %s -enable-machine-outliner -mtriple=aarch64-unknown-unknown -o /dev/null -pass-remarks-missed=machine-outliner -pass-remarks-output=%t.yaml
 ; RUN: cat %t.yaml | FileCheck %s -check-prefix=YAML
 ; YAML: --- !Missed
 ; YAML-NEXT: Pass:            machine-outliner
 ; YAML-NEXT: Name:            NotOutliningCheaper
 ; YAML-NEXT: DebugLoc:        { File: machine-outliner-remarks.ll, Line: 5, Column: 9 }
 ; YAML-NEXT: Function:        dog
 ; YAML-NEXT: Args:            

 ; YAML-NEXT: Pass:            machine-outliner
 ; YAML-NEXT: Name:            OutlinedFunction
 ; YAML-NEXT: Function:        OUTLINED_FUNCTION_0
 ; YAML-NEXT: Args:            
 ; YAML-NEXT:   - String:          'Saved '
 ; YAML-NEXT:   - OutliningBenefit: '5'
 ; YAML-NEXT:   - String:          ' instructions by '
 ; YAML-NEXT:   - String:          'outlining '
-; YAML-NEXT:   - Length:          '7'
+; YAML-NEXT:   - Length:          '12'
 ; YAML-NEXT:   - String:          ' instructions '
 ; YAML-NEXT:   - String:          'from '
 ; YAML-NEXT:   - NumOccurrences:  '2'
 ; YAML-NEXT:   - String:          ' locations. '
 ; YAML-NEXT:   - String:          '(Found at: '
-; YAML-NEXT:   - StartLoc0:       'machine-outliner-remarks.ll:27:9'
-; YAML-NEXT:     DebugLoc:        { File: machine-outliner-remarks.ll, Line: 27, Column: 9 }
-; YAML-NEXT:   - String:          ', '
-; YAML-NEXT:   - StartLoc1:       'machine-outliner-remarks.ll:36:1'
+; YAML-NEXT:   - StartLoc0:       'machine-outliner-remarks.ll:36:1'
 ; YAML-NEXT:     DebugLoc:        { File: machine-outliner-remarks.ll, Line: 36, Column: 1 }
+; YAML-NEXT:   - String:          ', '
+; YAML-NEXT:   - StartLoc1:       'machine-outliner-remarks.ll:27:9'
+; YAML-NEXT:     DebugLoc:        { File: machine-outliner-remarks.ll, Line: 27, Column: 9 }
 ; YAML-NEXT:   - String:          ')'
 
 define void @dog() #0 !dbg !8 {
 entry:
   %x = alloca i32, align 4
   %y = alloca i32, align 4
   store i32 0, i32* %x, align 4
   store i32 1, i32* %y, align 4, !dbg !12
entry:
   ret void
 }
 
 define void @foo() #0 !dbg !18 {
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
-  store i32 0, i32* %1, align 4
-  store i32 1, i32* %2, align 4, !dbg !24
-  store i32 2, i32* %3, align 4
-  store i32 3, i32* %4, align 4, !dbg !26
+  %5 = alloca i32, align 4
+  %6 = alloca i32, align 4
+  store i32 1, i32* %1, align 4, !dbg !24
+  store i32 2, i32* %2, align 4
+  store i32 3, i32* %3, align 4
+  store i32 4, i32* %4, align 4
+  store i32 5, i32* %5, align 4
+  store i32 6, i32* %6, align 4, !dbg !26
   ret void
 }
 
 define void @bar() #0 !dbg !27 {
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
-  store i32 0, i32* %1, align 4
-  store i32 1, i32* %2, align 4, !dbg !33
-  store i32 2, i32* %3, align 4
-  store i32 3, i32* %4, align 4, !dbg !35
+  %5 = alloca i32, align 4
+  %6 = alloca i32, align 4
+  store i32 1, i32* %1, align 4, !dbg !33
+  store i32 2, i32* %2, align 4
+  store i32 3, i32* %3, align 4
+  store i32 4, i32* %4, align 4
+  store i32 5, i32* %5, align 4
+  store i32 6, i32* %6, align 4, !dbg !35
   ret void
 }
 
 attributes #0 = { noredzone nounwind ssp uwtable "no-frame-pointer-elim"="false" "target-cpu"="cyclone" }
 
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!3, !4, !5, !6}
 !llvm.ident = !{!7}

test/CodeGen/AArch64/machine-outliner.ll

 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=aarch64-apple-darwin < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -enable-linkonceodr-outlining -mtriple=aarch64-apple-darwin < %s | FileCheck %s -check-prefix=ODR
 
 define linkonce_odr void @fish() #0 {
   ; CHECK-LABEL: _fish:
   ; CHECK-NOT: OUTLINED
   ; ODR: [[OUTLINED:OUTLINED_FUNCTION_[0-9]+]]
-  ; ODR-NOT: ret
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
-  store i32 0, i32* %1, align 4
-  store i32 1, i32* %2, align 4
-  store i32 2, i32* %3, align 4
-  store i32 3, i32* %4, align 4
+  %5 = alloca i32, align 4
+  %6 = alloca i32, align 4
+  store i32 1, i32* %1, align 4
+  store i32 2, i32* %2, align 4
+  store i32 3, i32* %3, align 4
+  store i32 4, i32* %4, align 4
+  store i32 5, i32* %5, align 4
+  store i32 6, i32* %6, align 4
   ret void
 }
 
 define void @turtle() section "TURTLE,turtle" {
   ; CHECK-LABEL: _turtle:
   ; ODR-LABEL: _turtle:
   ; CHECK-NOT: OUTLINED
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
-  store i32 0, i32* %1, align 4
-  store i32 1, i32* %2, align 4
-  store i32 2, i32* %3, align 4
-  store i32 3, i32* %4, align 4
+  %5 = alloca i32, align 4
+  %6 = alloca i32, align 4
+  store i32 1, i32* %1, align 4
+  store i32 2, i32* %2, align 4
+  store i32 3, i32* %3, align 4
+  store i32 4, i32* %4, align 4
+  store i32 5, i32* %5, align 4
+  store i32 6, i32* %6, align 4
   ret void
 }
 
 define void @cat() #0 {
   ; CHECK-LABEL: _cat:
   ; CHECK: [[OUTLINED:OUTLINED_FUNCTION_[0-9]+]]
   ; ODR: [[OUTLINED]]
-  ; CHECK-NOT: ret
-  ; ODR-NOT: ret
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
-  store i32 0, i32* %1, align 4
-  store i32 1, i32* %2, align 4
-  store i32 2, i32* %3, align 4
-  store i32 3, i32* %4, align 4
+  %5 = alloca i32, align 4
+  %6 = alloca i32, align 4
+  store i32 1, i32* %1, align 4
+  store i32 2, i32* %2, align 4
+  store i32 3, i32* %3, align 4
+  store i32 4, i32* %4, align 4
+  store i32 5, i32* %5, align 4
+  store i32 6, i32* %6, align 4
   ret void
 }
 
 define void @dog() #0 {
   ; CHECK-LABEL: _dog:
   ; CHECK: [[OUTLINED]]
   ; ODR: [[OUTLINED]]
-  ; CHECK-NOT: ret
-  ; ODR-NOT: ret
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
-  store i32 0, i32* %1, align 4
-  store i32 1, i32* %2, align 4
-  store i32 2, i32* %3, align 4
-  store i32 3, i32* %4, align 4
+  %5 = alloca i32, align 4
+  %6 = alloca i32, align 4
+  store i32 1, i32* %1, align 4
+  store i32 2, i32* %2, align 4
+  store i32 3, i32* %3, align 4
+  store i32 4, i32* %4, align 4
+  store i32 5, i32* %5, align 4
+  store i32 6, i32* %6, align 4
   ret void
 }
 
 ; ODR: [[OUTLINED]]:
 ; CHECK: [[OUTLINED]]:
-; CHECK-DAG: orr w8, wzr, #0x1
-; CHECK-NEXT: stp w8, wzr, [sp, #8]
-; CHECK-NEXT: orr w8, wzr, #0x2
-; CHECK-NEXT: str w8, [sp, #4]
-; CHECK-NEXT: orr w8, wzr, #0x3
-; CHECK-NEXT: str w8, [sp], #16
+; CHECK: orr     w8, wzr, #0x1
+; CHECK-NEXT: str     w8, [sp, #44]
+; CHECK-NEXT: orr     w8, wzr, #0x2
+; CHECK-NEXT: str     w8, [sp, #40]
+; CHECK-NEXT: orr     w8, wzr, #0x3
+; CHECK-NEXT: str     w8, [sp, #36]
+; CHECK-NEXT: orr     w8, wzr, #0x4
+; CHECK-NEXT: str     w8, [sp, #32]
+; CHECK-NEXT: mov     w8, #5
+; CHECK-NEXT: str     w8, [sp, #28]
+; CHECK-NEXT: orr     w8, wzr, #0x6
+; CHECK-NEXT: str     w8, [sp, #24]
 ; CHECK-NEXT: ret
 
 attributes #0 = { noredzone "target-cpu"="cyclone" }