[mips] Don't use odd-numbered single precision registers for fastcc calling convention if -mno-odd-spreg is used.

[sstankovic]

Summary

[mips] Don't use odd-numbered single precision registers for fastcc calling convention if -mno-odd-spreg is used.

[dsanders]

LGTM, with a nit

I'll merge it to the branch once it's committed since it fixes the last of the MIPS32r6/MIPS64r6 test-suite failures.

test/CodeGen/Mips/fastcc.ll

300–302

It's because FileCheck scans ahead for ']]' which leaves the pattern as 'f[0-9]*[02468'. I usually work around it using a '+' like so:

$[[F0:f[0-9]*[02468]+]]

I can't explain why the other one works though. Triple ']' has never worked correctly for me.

357

Nit: Change the ']]]' to ']+]]' since we don't understand why this particular case works when all other cases of ']]]' we've encountered result in invalid regexes

[sstankovic]

I tried $[[F0:f[0-9]*[02468]+]] but it also doesn't work. It seems that problem is related to using DAG in check lines. I removed DAG from the last 3 lines, used $[[F0:f[0-9]*[02468]]] pattern and the test passes.

[dsanders]

In D4682#8, @sstankovic wrote:

I tried $[[F0:f[0-9]*[02468]+]] but it also doesn't work. It seems that problem is related to using DAG in check lines. I removed DAG from the last 3 lines, used $[[F0:f[0-9]*[02468]]] pattern and the test passes.

I've explained the current problem below. To be clear, I think you are ok to commit as-is. If it's possible to follow-up to make the test more robust then we should do so. Unique-ing the output instructions using different offsets is a good way to do this but I've found cases before where it's not sufficient (one of the calling convention tests has the same problem).

test/CodeGen/Mips/fastcc.ll

300–302

I think I see why this didn't work. It seems that the directive on line 303 is matching the first lwc1 in the code below:

lw      $1, %got(gfa8)($gp)
lwc1    $f16, 0($1)
...
lw      $1, %got(gfa10)($gp)
lwc1    $f20, 0($1)

The reason I think this happens is that IIRC, all the *-DAG directives start their search from the same point (the directive on line 273). There's nothing making the lines unique so line 295 and line 303 match in the same place. This leaves F0 set to the wrong register, line 304 fails to match, and the test is reported to fail.

There are two solutions to this. The first is make each line unique using different offsets into an array instead of using multiple global variables. The second is the way you've done it: Use something other than *-DAG to advance the current position past the unintended match.

If the above is correct, then I'm inclined to think that FileCheck ought to be accounting for the topography earlier. In particular, variable uses ought to start matching from the end of the directive containing the definition (instead of from the end of the previous non-*-DAG directive). However, changing that is likely to be hard and it's difficult to say whether there are tests depending on the current behaviour or not.

[sstankovic]

I replaced global variables with the array. This actually makes CHECKS much simpler.

[dsanders]

LGTM, Thanks.

[sstankovic]

Closed by commit rL214180 (authored by @sstankovic).

lib/Target/Mips/MipsCallingConv.td

def CC_Mips_FastCC : CallingConv<[
   // In NaCl, T6, T7 and T8 are reserved and not available as argument
   // registers for fastcc.  T6 contains the mask for sandboxing control flow
   // (indirect jumps and calls).  T7 contains the mask for sandboxing memory
   // accesses (loads and stores).  T8 contains the thread pointer.
   CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
       CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
 
   // f32 arguments are passed in single-precision floating pointer registers.
-  CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10,
-                                 F11, F12, F13, F14, F15, F16, F17, F18, F19]>>,
+  CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
+      CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
+                     F14, F15, F16, F17, F18, F19]>>>,
+
+  // Don't use odd numbered single-precision registers for -mno-odd-spreg.
+  CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
+      CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
 
   // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
   CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
 
   CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
   CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
   CCDelegateTo<CC_MipsN_FastCC>
 ]>;

lib/Target/Mips/MipsSubtarget.h

public:
   bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
 
   bool hasCnMips() const { return HasCnMips; }
 
   bool isLittle() const { return IsLittle; }
   bool isFPXX() const { return IsFPXX; }
   bool isFP64bit() const { return IsFP64bit; }
   bool useOddSPReg() const { return UseOddSPReg; }
+  bool noOddSPReg() const { return !UseOddSPReg; }
   bool isNaN2008() const { return IsNaN2008bit; }
   bool isNotFP64bit() const { return !IsFP64bit; }
   bool isGP64bit() const { return IsGP64bit; }
   bool isGP32bit() const { return !IsGP64bit; }
   bool isSingleFloat() const { return IsSingleFloat; }
   bool isNotSingleFloat() const { return !IsSingleFloat; }
   bool hasVFPU() const { return HasVFPU; }
   bool inMips16Mode() const { return InMips16Mode; }

test/CodeGen/Mips/fastcc.ll

 ; RUN: llc  < %s -march=mipsel | FileCheck %s 
 ; RUN: llc  < %s -mtriple=mipsel-none-nacl-gnu \
 ; RUN:  | FileCheck %s -check-prefix=CHECK-NACL
+; RUN: llc  < %s -march=mipsel -mcpu=mips32 -mattr=+nooddspreg | FileCheck %s -check-prefix=NOODDSPREG
 
 
 @gi0 = external global i32
 @gi1 = external global i32
 @gi2 = external global i32
 @gi3 = external global i32
 @gi4 = external global i32
 @gi5 = external global i32
; CHECK: swc1  $f19
   store float %a16, float* @gf16, align 4
   store float %a17, float* @gf17, align 4
   store float %a18, float* @gf18, align 4
   store float %a19, float* @gf19, align 4
   store float %a20, float* @gf20, align 4
   ret void
 }
 
+define void @caller2(float %a0, float %a1, float %a2, float %a3, float %a4,
+                     float %a5, float %a6, float %a7, float %a8, float %a9,
+                     float %a10) {
+entry:
+
+; NOODDSPREG-LABEL:  caller2
+
+; Check that first 10 arguments are passed in even float registers
+; f0, f2, ... , f18. Check that 11th argument is passed on stack.
+
+; NOODDSPREG-DAG:    lw $[[R0:[0-9]+]], %got(gfa0)($[[GP:[0-9]+|gp]])
+; NOODDSPREG-DAG:    lwc1 $f0, 0($[[R0]])
+; NOODDSPREG-DAG:    lw $[[R0:[0-9]+]], %got(gfa1)($[[GP]])
+; NOODDSPREG-DAG:    lwc1 $f2, 0($[[R0]])
+; NOODDSPREG-DAG:    lw $[[R0:[0-9]+]], %got(gfa2)($[[GP]])
+; NOODDSPREG-DAG:    lwc1 $f4, 0($[[R0]])
+; NOODDSPREG-DAG:    lw $[[R0:[0-9]+]], %got(gfa3)($[[GP]])
+; NOODDSPREG-DAG:    lwc1 $f6, 0($[[R0]])
+; NOODDSPREG-DAG:    lw $[[R0:[0-9]+]], %got(gfa4)($[[GP]])
+; NOODDSPREG-DAG:    lwc1 $f8, 0($[[R0]])
+; NOODDSPREG-DAG:    lw $[[R0:[0-9]+]], %got(gfa5)($[[GP]])
+; NOODDSPREG-DAG:    lwc1 $f10, 0($[[R0]])
+; NOODDSPREG-DAG:    lw $[[R0:[0-9]+]], %got(gfa6)($[[GP]])
+; NOODDSPREG-DAG:    lwc1 $f12, 0($[[R0]])
+; NOODDSPREG-DAG:    lw $[[R0:[0-9]+]], %got(gfa7)($[[GP]])
+; NOODDSPREG-DAG:    lwc1 $f14, 0($[[R0]])
+; NOODDSPREG-DAG:    lw $[[R0:[0-9]+]], %got(gfa8)($[[GP]])
+; NOODDSPREG-DAG:    lwc1 $f16, 0($[[R0]])
+; NOODDSPREG-DAG:    lw $[[R0:[0-9]+]], %got(gfa9)($[[GP]])
+; NOODDSPREG-DAG:    lwc1 $f18, 0($[[R0]])
+
+; I omitted DAG from the following 3 lines because otherwise the pattern
+; $[[F0:f[0-9]*[02468]]] for even float registers doesn't work for some
+; reason (it works below in callee2). Alternatively, if DAG has to be used,
+; the pattern can be replaced with $[[F0:f20|f22|f24|f26|f28|f30]].
+; NOODDSPREG:        lw $[[R0:[0-9]+]], %got(gfa10)($[[GP]])
+; NOODDSPREG:        lwc1 $[[F0:f[0-9]*[02468]]], 0($[[R0]])
+; NOODDSPREG:        swc1 $[[F0]], 0($sp)
+
+  %0 = load float* @gfa0, align 4
+  %1 = load float* @gfa1, align 4
+  %2 = load float* @gfa2, align 4
+  %3 = load float* @gfa3, align 4
+  %4 = load float* @gfa4, align 4
+  %5 = load float* @gfa5, align 4
+  %6 = load float* @gfa6, align 4
+  %7 = load float* @gfa7, align 4
+  %8 = load float* @gfa8, align 4
+  %9 = load float* @gfa9, align 4
+  %10 = load float* @gfa10, align 4
+  tail call fastcc void @callee2(float %0, float %1, float %2, float %3,
+                                 float %4, float %5, float %6, float %7,
+                                 float %8, float %9, float %10)
+  ret void
+}
+
+define fastcc void @callee2(float %a0, float %a1, float %a2, float %a3,
+                            float %a4, float %a5, float %a6, float %a7,
+                            float %a8, float %a9, float %a10) {
+entry:
+
+; NOODDSPREG-LABEL:  callee2
+
+; NOODDSPREG:        addiu   $sp, $sp, -[[OFFSET:[0-9]+]]
+
+; Check that first 10 arguments are received in even float registers
+; f0, f2, ... , f18. Check that 11th argument is received on stack.
+
+; NOODDSPREG-DAG:    lw      $[[R0:[0-9]+]], %got(gf0)($[[GP:[0-9]+|gp]])
+; NOODDSPREG-DAG:    swc1    $f0, 0($[[R0]])
+; NOODDSPREG-DAG:    lw      $[[R0:[0-9]+]], %got(gf1)($[[GP]])
+; NOODDSPREG-DAG:    swc1    $f2, 0($[[R0]])
+; NOODDSPREG-DAG:    lw      $[[R0:[0-9]+]], %got(gf2)($[[GP]])
+; NOODDSPREG-DAG:    swc1    $f4, 0($[[R0]])
+; NOODDSPREG-DAG:    lw      $[[R0:[0-9]+]], %got(gf3)($[[GP]])
+; NOODDSPREG-DAG:    swc1    $f6, 0($[[R0]])
+; NOODDSPREG-DAG:    lw      $[[R0:[0-9]+]], %got(gf4)($[[GP]])
+; NOODDSPREG-DAG:    swc1    $f8, 0($[[R0]])
+; NOODDSPREG-DAG:    lw      $[[R0:[0-9]+]], %got(gf5)($[[GP]])
+; NOODDSPREG-DAG:    swc1    $f10, 0($[[R0]])
+; NOODDSPREG-DAG:    lw      $[[R0:[0-9]+]], %got(gf6)($[[GP]])
+; NOODDSPREG-DAG:    swc1    $f12, 0($[[R0]])
+; NOODDSPREG-DAG:    lw      $[[R0:[0-9]+]], %got(gf7)($[[GP]])
+; NOODDSPREG-DAG:    swc1    $f14, 0($[[R0]])
+; NOODDSPREG-DAG:    lw      $[[R0:[0-9]+]], %got(gf8)($[[GP]])
+; NOODDSPREG-DAG:    swc1    $f16, 0($[[R0]])
+; NOODDSPREG-DAG:    lw      $[[R0:[0-9]+]], %got(gf9)($[[GP]])
+; NOODDSPREG-DAG:    swc1    $f18, 0($[[R0]])
+
+; NOODDSPREG-DAG:    lw      $[[R0:[0-9]+]], %got(gf10)($[[GP]])
+; NOODDSPREG-DAG:    lwc1    $[[F0:f[0-9]*[02468]]], [[OFFSET]]($sp)
+; NOODDSPREG-DAG:    swc1    $[[F0]], 0($[[R0]])
+
+  store float %a0, float* @gf0, align 4
+  store float %a1, float* @gf1, align 4
+  store float %a2, float* @gf2, align 4
+  store float %a3, float* @gf3, align 4
+  store float %a4, float* @gf4, align 4
+  store float %a5, float* @gf5, align 4
+  store float %a6, float* @gf6, align 4
+  store float %a7, float* @gf7, align 4
+  store float %a8, float* @gf8, align 4
+  store float %a9, float* @gf9, align 4
+  store float %a10, float* @gf10, align 4
+  ret void
+}
+