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Differential D46536

[Power9]Legalize and emit code for W vector extract and convert to Quad-Precision
ClosedPublic

Authored by lei on May 7 2018, 10:59 AM.

Details

Reviewers
nemanjai
kbarton
hfinkel
Commits
rG8b0da65bfba3: [Power9]Legalize and emit code for W vector extract and convert to QP
rL333115: [Power9]Legalize and emit code for W vector extract and convert to QP
Summary

Implemente patterns to extract W vector elements and convert to QP

Diff Detail

Repository
rL LLVM

Event Timeline

lei created this revision.May 7 2018, 10:59 AM
lei updated this revision to Diff 146270.May 10 2018, 7:21 PM
nemanjai requested changes to this revision.May 11 2018, 4:30 AM

I think we should review the code sequences for signed conversions and make more consistent use of loops.

lib/Target/PowerPC/PPCInstrVSX.td
3165 ↗(On Diff #146270)

This probably needs let Predicates = [IsBigEndian, HasP9Vector] right?

3168 ↗(On Diff #146270)

Is this sequence actually correct? We convert a vector of 4 4-byte integers into a vector of 2 8-byte double precision floating point values. Then we treat it as a signed 8-byte integer and convert it to a 16-byte floating point value. Shouldn't the outer instruction be xscvdpqp?

In any case, vextsw2d -> xscvsdqp is a much lower latency sequence than this. Why not use that?

3176 ↗(On Diff #146270)

Is there no mul function in TableGen? i.e. can't we just write !mul(Idx, 4)?

3194 ↗(On Diff #146270)

Same note regarding the predicate.

3196 ↗(On Diff #146270)

To be consistent, I think you should write these as a neat for-loop as you did above. The element would be Idx and the splat index would be !sub(3, Idx). Wouldn't that work?

3207 ↗(On Diff #146270)

Same thing here, a for-loop would be nicer and more consistent.

This revision now requires changes to proceed.May 11 2018, 4:30 AM
lei added inline comments.May 11 2018, 6:55 AM
lib/Target/PowerPC/PPCInstrVSX.td
3165 ↗(On Diff #146270)

This is within a Predicates = [HasP9Vector] section so is not needed here.

3168 ↗(On Diff #146270)

I guess there is no need for us to convert to double precision here. Will update.

3176 ↗(On Diff #146270)

There is only !add(a,b,...)

3194 ↗(On Diff #146270)

this is within a Predicates = [HasP9Vector] code section.

3196 ↗(On Diff #146270)

Unfortunately there is no !sub() operator.

3207 ↗(On Diff #146270)

I agree. I just couldn't find a way to do it with just !add()

lei added inline comments.May 11 2018, 8:22 AM
lib/Target/PowerPC/PPCInstrVSX.td
3165 ↗(On Diff #146270)

will add!

3194 ↗(On Diff #146270)

will add!

lei updated this revision to Diff 146364.May 11 2018, 11:10 AM
lei marked 2 inline comments as done.

This should address all review comments.

lei updated this revision to Diff 146407.May 11 2018, 1:46 PM
lei marked an inline comment as done and an inline comment as not done.

Update to use foreach loop for LE patterns.

nemanjai added inline comments.May 14 2018, 5:37 AM
lib/Target/PowerPC/PPCInstrVSX.td
3167 ↗(On Diff #146407)

It is actually word 1 that doesn't need the splat. Word 0 does need a splat.

3196 ↗(On Diff #146407)

This should actually be foreach Idx = [[0,3],[1,2],[3,0]] shouldn't it? For LE word element 2, VEXTSW2D will sign extend it into LE doubleword element 1 which is where XSCVSDQP needs it to be - so a splat is not needed. LE word element 3 on the other hand will need a splat since the input is in the left half of LE doubleword 1 and it needs to be in the right half.

lei updated this revision to Diff 146597.May 14 2018, 6:59 AM

Address review comments

lei marked 3 inline comments as done.May 14 2018, 6:59 AM
lei added inline comments.
lib/Target/PowerPC/PPCInstrVSX.td
3167 ↗(On Diff #146407)

You are right!

3196 ↗(On Diff #146407)

Yes. This is true... I forgot to check this when I switched xvcvsxwdp for vextsw2d.

nemanjai accepted this revision.May 18 2018, 6:41 AM

LGTM. Feel free to address the minor nit on the commit.

lib/Target/PowerPC/PPCInstrVSX.td
3202 ↗(On Diff #146597)

Nit: For consistency, move this up before the loop since that's the order of definitions in the big-endian block above.

This revision is now accepted and ready to land.May 18 2018, 6:41 AM
Closed by commit rL333115: [Power9]Legalize and emit code for W vector extract and convert to QP (authored by lei). · Explain WhyMay 23 2018, 12:35 PM
This revision was automatically updated to reflect the committed changes.
lei marked 2 inline comments as done.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
PowerPC/
42 lines
test/
CodeGen/
PowerPC/
181 lines

Diff 148269

llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td

Show First 20 Lines • Show All 3,146 Lines • ▼ Show 20 Lines def DFSTOREf64 : Pseudo<(outs), (ins vsfrc:$XT, memrix:$dst),
"#DFSTOREf64", "#DFSTOREf64",
[(store f64:$XT, ixaddr:$dst)]>; [(store f64:$XT, ixaddr:$dst)]>;
} }
def : Pat<(f64 (extloadf32 ixaddr:$src)), def : Pat<(f64 (extloadf32 ixaddr:$src)),
(COPY_TO_REGCLASS (DFLOADf32 ixaddr:$src), VSFRC)>; (COPY_TO_REGCLASS (DFLOADf32 ixaddr:$src), VSFRC)>;
def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))), def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))),
(f32 (DFLOADf32 ixaddr:$src))>; (f32 (DFLOADf32 ixaddr:$src))>;
let Predicates = [IsBigEndian, HasP9Vector] in {
// (Un)Signed DWord vector extract -> QP // (Un)Signed DWord vector extract -> QP
let Predicates = [IsBigEndian] in {
def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))), def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),
(f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))), def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),
(f128 (XSCVSDQP (f128 (XSCVSDQP
(EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))), def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),
(f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))), def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),
(f128 (XSCVUDQP (f128 (XSCVUDQP
(EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
// (Un)Signed Word vector extract -> QP
def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 1)))),
(f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>;
foreach Idx = [0,2,3] in {
def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, Idx)))),
(f128 (XSCVSDQP (EXTRACT_SUBREG
(VEXTSW2D (VSPLTW Idx, $src)), sub_64)))>;
}
foreach Idx = 0-3 in {
def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, Idx)))),
(f128 (XSCVUDQP (XXEXTRACTUW $src, !shl(Idx, 2))))>;
} }
let Predicates = [IsLittleEndian] in { } // IsBigEndian, HasP9Vector
let Predicates = [IsLittleEndian, HasP9Vector] in {
// (Un)Signed DWord vector extract -> QP
def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))), def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),
(f128 (XSCVSDQP (f128 (XSCVSDQP
(EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))), def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),
(f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))), def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),
(f128 (XSCVUDQP (f128 (XSCVUDQP
(EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))), def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),
(f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
// (Un)Signed Word vector extract -> QP
foreach Idx = [[0,3],[1,2],[3,0]] in {
def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))),
(f128 (XSCVSDQP (EXTRACT_SUBREG
(VEXTSW2D (VSPLTW !head(!tail(Idx)), $src)),
sub_64)))>;
} }
def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 2)))),
(f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>;
foreach Idx = [[0,12],[1,8],[2,4],[3,0]] in {
def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))),
(f128 (XSCVUDQP (XXEXTRACTUW $src, !head(!tail(Idx)))))>;
}
} // IsLittleEndian, HasP9Vector
// Convert (Un)Signed DWord in memory -> QP // Convert (Un)Signed DWord in memory -> QP
def : Pat<(f128 (sint_to_fp (i64 (load xaddr:$src)))), def : Pat<(f128 (sint_to_fp (i64 (load xaddr:$src)))),
(f128 (XSCVSDQP (LXSDX xaddr:$src)))>; (f128 (XSCVSDQP (LXSDX xaddr:$src)))>;
def : Pat<(f128 (sint_to_fp (i64 (load ixaddr:$src)))), def : Pat<(f128 (sint_to_fp (i64 (load ixaddr:$src)))),
(f128 (XSCVSDQP (LXSD ixaddr:$src)))>; (f128 (XSCVSDQP (LXSD ixaddr:$src)))>;
def : Pat<(f128 (uint_to_fp (i64 (load xaddr:$src)))), def : Pat<(f128 (uint_to_fp (i64 (load xaddr:$src)))),
(f128 (XSCVUDQP (LXSDX xaddr:$src)))>; (f128 (XSCVUDQP (LXSDX xaddr:$src)))>;
▲ Show 20 Lines • Show All 469 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/PowerPC/f128-vecExtractNconv.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -verify-machineinstrs -enable-ppc-quad-precision < %s | FileCheck %s ; RUN: -verify-machineinstrs -enable-ppc-quad-precision < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
; RUN: -verify-machineinstrs -enable-ppc-quad-precision < %s | \ ; RUN: -verify-machineinstrs -enable-ppc-quad-precision < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-BE ; RUN: FileCheck %s -check-prefix=CHECK-BE
; Vector extract DWord and convert to quad precision.
@sdwVecMem = global <2 x i64> <i64 88, i64 99>, align 16 @sdwVecMem = global <2 x i64> <i64 88, i64 99>, align 16
@udwVecMem = global <2 x i64> <i64 88, i64 99>, align 16 @udwVecMem = global <2 x i64> <i64 88, i64 99>, align 16
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @sdwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) { define void @sdwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) {
; CHECK-LABEL: sdwVecConv2qp: ; CHECK-LABEL: sdwVecConv2qp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxspltd 34, 34, 1 ; CHECK-NEXT: xxspltd 34, 34, 1
▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load <2 x i64>, <2 x i64>* %b, align 16 %0 = load <2 x i64>, <2 x i64>* %b, align 16
%vecext = extractelement <2 x i64> %0, i32 0 %vecext = extractelement <2 x i64> %0, i32 0
%conv = uitofp i64 %vecext to fp128 %conv = uitofp i64 %vecext to fp128
store fp128 %conv, fp128* %a, align 16 store fp128 %conv, fp128* %a, align 16
ret void ret void
} }
; Vector extract Word and convert to quad precision.
@swVecMem = global <4 x i32> <i32 88, i32 99, i32 100, i32 2>, align 16
@uwVecMem = global <4 x i32> <i32 89, i32 89, i32 200, i32 3>, align 16
; Function Attrs: norecurse nounwind
define void @swVecConv2qp(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: swVecConv2qp:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vspltw 2, 2, 3
; CHECK-NEXT: vextsw2d 2, 2
; CHECK-NEXT: xscvsdqp 2, 2
; CHECK-NEXT: stxv 34, 0(3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: swVecConv2qp:
; CHECK-BE: vspltw 2, 2, 0
; CHECK-BE-NEXT: vextsw2d 2, 2
; CHECK-BE-NEXT: xscvsdqp 2, 2
; CHECK-BE-NEXT: stxv 34, 0(3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 0
%conv = sitofp i32 %vecext to fp128
store fp128 %conv, fp128* %a, align 16
ret void
}
; Function Attrs: norecurse nounwind
define void @swVecConv2qp1(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: swVecConv2qp1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vspltw 2, 2, 2
; CHECK-NEXT: vextsw2d 2, 2
; CHECK-NEXT: xscvsdqp 2, 2
; CHECK-NEXT: stxv 34, 0(3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: swVecConv2qp1:
; CHECK-BE: vextsw2d 2, 2
; CHECK-BE-NEXT: xscvsdqp 2, 2
; CHECK-BE-NEXT: stxv 34, 0(3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 1
%conv = sitofp i32 %vecext to fp128
store fp128 %conv, fp128* %a, align 16
ret void
}
; Function Attrs: norecurse nounwind
define void @swVecConv2qp2(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: swVecConv2qp2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vextsw2d 2, 2
; CHECK-NEXT: xscvsdqp 2, 2
; CHECK-NEXT: stxv 34, 0(3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: swVecConv2qp2:
; CHECK-BE: vspltw 2, 2, 2
; CHECK-BE-NEXT: vextsw2d 2, 2
; CHECK-BE-NEXT: xscvsdqp 2, 2
; CHECK-BE-NEXT: stxv 34, 0(3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 2
%conv = sitofp i32 %vecext to fp128
store fp128 %conv, fp128* %a, align 16
ret void
}
; Function Attrs: norecurse nounwind
define void @swVecConv2qp3(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: swVecConv2qp3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vspltw 2, 2, 0
; CHECK-NEXT: vextsw2d 2, 2
; CHECK-NEXT: xscvsdqp 2, 2
; CHECK-NEXT: stxv 34, 0(3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: swVecConv2qp3:
; CHECK-BE: vspltw 2, 2, 3
; CHECK-BE-NEXT: vextsw2d 2, 2
; CHECK-BE-NEXT: xscvsdqp 2, 2
; CHECK-BE-NEXT: stxv 34, 0(3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 3
%conv = sitofp i32 %vecext to fp128
store fp128 %conv, fp128* %a, align 16
ret void
}
; Function Attrs: norecurse nounwind
define void @uwVecConv2qp(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: uwVecConv2qp:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxextractuw 34, 34, 12
; CHECK-NEXT: xscvudqp 2, 2
; CHECK-NEXT: stxv 34, 0(3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: uwVecConv2qp:
; CHECK-BE: xxextractuw 34, 34, 0
; CHECK-BE-NEXT: xscvudqp 2, 2
; CHECK-BE-NEXT: stxv 34, 0(3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 0
%conv = uitofp i32 %vecext to fp128
store fp128 %conv, fp128* %a, align 16
ret void
}
; Function Attrs: norecurse nounwind
define void @uwVecConv2qp1(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: uwVecConv2qp1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxextractuw 34, 34, 8
; CHECK-NEXT: xscvudqp 2, 2
; CHECK-NEXT: stxv 34, 0(3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: uwVecConv2qp1:
; CHECK-BE: xxextractuw 34, 34, 4
; CHECK-BE-NEXT: xscvudqp 2, 2
; CHECK-BE-NEXT: stxv 34, 0(3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 1
%conv = uitofp i32 %vecext to fp128
store fp128 %conv, fp128* %a, align 16
ret void
}
; Function Attrs: norecurse nounwind
define void @uwVecConv2qp2(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: uwVecConv2qp2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxextractuw 34, 34, 4
; CHECK-NEXT: xscvudqp 2, 2
; CHECK-NEXT: stxv 34, 0(3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: uwVecConv2qp2:
; CHECK-BE: xxextractuw 34, 34, 8
; CHECK-BE-NEXT: xscvudqp 2, 2
; CHECK-BE-NEXT: stxv 34, 0(3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 2
%conv = uitofp i32 %vecext to fp128
store fp128 %conv, fp128* %a, align 16
ret void
}
; Function Attrs: norecurse nounwind
define void @uwVecConv2qp3(fp128* nocapture %a, <4 x i32> %b) {
; CHECK-LABEL: uwVecConv2qp3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxextractuw 34, 34, 0
; CHECK-NEXT: xscvudqp 2, 2
; CHECK-NEXT: stxv 34, 0(3)
; CHECK-NEXT: blr
; CHECK-BE-LABEL: uwVecConv2qp3:
; CHECK-BE: xxextractuw 34, 34, 12
; CHECK-BE-NEXT: xscvudqp 2, 2
; CHECK-BE-NEXT: stxv 34, 0(3)
; CHECK-BE-NEXT: blr
entry:
%vecext = extractelement <4 x i32> %b, i32 3
%conv = uitofp i32 %vecext to fp128
store fp128 %conv, fp128* %a, align 16
ret void
}