Revert "This pass, fixing an erratum in some LEON 2 processors..."

[dcederman]

Summary

Reading Atmel's AT697E errata document this does not seem like a valid workaround. While the text only mentions SDIV, it says that the ICC flags can be wrong, and those are only generated by SDIVcc. Verification on hardware shows that simply replacing SDIV with SDIVcc does not avoid the bug with negative operands.

This reverts r283727.

llvm/trunk/lib/Target/Sparc/LeonFeatures.td

 //support to casa instruction; for leon3 subtarget only
 def LeonCASA : SubtargetFeature<
   "hasleoncasa", 
   "HasLeonCasa", 
   "true", 
   "Enable CASA instruction for LEON3 and LEON4 processors"
 >;
 
-
-def ReplaceSDIV : SubtargetFeature<
-  "replacesdiv",
-  "PerformSDIVReplace",
-  "true",
-  "AT697E erratum fix: Do not emit SDIV, emit SDIVCC instead"
->;
-          
 def InsertNOPLoad: SubtargetFeature<
   "insertnopload",
   "InsertNOPLoad",
   "true",
   "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction" 
 >;
 
 def DetectRoundChange : SubtargetFeature<

llvm/trunk/lib/Target/Sparc/Sparc.td

 
 // LEON 2 FT generic
 def : Processor<"leon2", LEON2Itineraries,
                 [FeatureLeon]>;
 
 // LEON 2 FT (AT697E)
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"at697e", LEON2Itineraries,
-                [FeatureLeon, ReplaceSDIV, InsertNOPLoad]>;
+                [FeatureLeon, InsertNOPLoad]>;
 
 // LEON 2 FT (AT697F)
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"at697f", LEON2Itineraries,
                 [FeatureLeon, InsertNOPLoad]>;
 
 
 // LEON 3 FT generic

llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp

if (N->getOpcode() == ISD::SDIV) {
       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
     }
     TopPart = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SP::Y, TopPart,
                                    SDValue())
                   .getValue(1);
 
     // FIXME: Handle div by immediate.
     unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
-    // SDIV is a hardware erratum on some LEON2 processors. Replace it with SDIVcc here.
-    if (((SparcTargetMachine&)TM).getSubtargetImpl()->performSDIVReplace()
-        &&
-        Opcode == SP::SDIVrr) {
-      Opcode = SP::SDIVCCrr;
-    }
     CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
     return;
   }
   }
 
   SelectCode(N);
 }
 

llvm/trunk/lib/Target/Sparc/SparcSubtarget.h

class SparcSubtarget : public SparcGenSubtargetInfo {
   bool HasNoFMULS;
 
   // LEON features
   bool HasUmacSmac;
   bool HasLeonCasa;
   bool InsertNOPLoad;
   bool FixAllFDIVSQRT;
   bool DetectRoundChange;
-  bool PerformSDIVReplace;
 
   SparcInstrInfo InstrInfo;
   SparcTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
   SparcFrameLowering FrameLowering;
 
 public:
   SparcSubtarget(const Triple &TT, const std::string &CPU,
public:
   bool hasHardQuad() const { return HasHardQuad; }
   bool usePopc() const { return UsePopc; }
   bool useSoftFloat() const { return UseSoftFloat; }
   bool hasNoFSMULD() const { return HasNoFSMULD; }
   bool hasNoFMULS() const { return HasNoFMULS; }
 
   // Leon options
   bool hasUmacSmac() const { return HasUmacSmac; }
-  bool performSDIVReplace() const { return PerformSDIVReplace; }
   bool hasLeonCasa() const { return HasLeonCasa; }
   bool insertNOPLoad() const { return InsertNOPLoad; }
   bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; }
   bool detectRoundChange() const { return DetectRoundChange; }
 
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);

llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp

SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
   UsePopc = false;
   UseSoftFloat = false;
   HasNoFSMULD = false;
   HasNoFMULS = false;
 
   // Leon features
   HasLeonCasa = false;
   HasUmacSmac = false;
-  PerformSDIVReplace = false;
   InsertNOPLoad = false;
   FixAllFDIVSQRT = false;
   DetectRoundChange = false;
 
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = (Is64Bit) ? "v9" : "v8";

llvm/trunk/test/CodeGen/SPARC/LeonReplaceSDIVPassUT.ll

-; RUN: llc %s -O0 -march=sparc -o - | FileCheck %s -check-prefix=NO_REPLACE_SDIV
-; RUN: llc %s -O0 -march=sparc -mcpu=at697e -o - | FileCheck %s -check-prefix=REPLACE_SDIV
-
-; REPLACE_SDIV: sdivcc %o0, %o1, %o0
-; NO_REPLACE_SDIV: sdiv %o0, %o1, %o0
-
-define i32 @lbr59(i32 %a, i32 %b)
-{
-  %r = sdiv i32 %a, %b
-  ret i32 %r 
-}